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m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers description these are single-chip microcomputers designed with high-perfor- mance cmos silicon gate technology, including the internal flash memory. these microcomputers support the 7900 series instruction set, which are enhanced and expanded instruction set and are up- per-compatible with the 7700/7751 series instruction set. the cpu of these microcomputers is a 16-bit parallel processor that can also be switched to perform 8-bit parallel processing. also, the bus interface unit of these microcomputers enhances the memory access efficiency to execute instructions fast. therefore, these mi- crocomputers are suitable for office, business, and industrial equip- ment controller that require high-speed processing of large data. for the internal flash memory, single-power-supply programming and erasure, using a prom programmer or the control by the cen- tral processing unit (cpu), is supported. also, each of these micro- computers has the memory area dedicated for storing a certain software which controls programming and erasure (reprogramming control software). therefore, on these microcomputers, the program can easily be changed even after they are mounted on the board. distinctive features number of basic machine instructions .................................... 203 memory [m37902fcchp] flash memory (user rom area) ................................. 120 kbytes ram ............................................................................. 4096 bytes [m37902fgchp] flash memory (user rom area) ................................. 248 kbytes ram ............................................................................. 6144 bytes [m37902fjchp] flash memory (user rom area) ................................. 498 kbytes ram ........................................................................... 12288 bytes [all of the above computers] flash memory (boot rom area) ................................... 16 kbytes instruction execution time the fastest instruction at 26 mhz frequency ........................ 38 ns single power supply .................................................... 5 v ?0.5 v interrupts ........... 6 external sources, 16 internal sources, 7 levels multi-functional 16-bit timer ................................................... 5 + 3 serial i/o (uart or clock synchronous) ..................................... 2 10-bit a-d converter ............................................ 8-channel inputs 8-bit d-a converter ............................................ 3-channel outputs real-time output .... 4 bits 2 channels, or 6 bits 1 channel + 2 bits 1 channel 12-bit watchdog timer programmable input/output (ports p0?8, p10, p11) ............... 84 power supply voltage .................................................. 5 v ?0.5 v programming/erase voltage ........................................ 5 v ?0.5 v programming method ............ programming in a unit of 256 bytes erase method ............................................ block erase or total erase (data protection per block is enabled.) programming/erase control by software command maximum number of reprograms ............................................ 100 application control devices for personal computer peripheral equipment such as cd-rom drives, dvd-rom drives, hard disk drives, high density fdd, printers
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 2 m37902fxchp pin configuration (top view) outline 100p6q-a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 p6 4 /int 2 ? p6 3 /int 1 ? p6 2 /int 0 ? p6 1 /ta4 in ? p6 0 /ta4 out ? p5 5 /ta2 in /rtp1 1 /ki 1 ? p5 4 /ta2 out /rtp1 0 /ki 0 ? p5 3 /ta1 in /rtp0 3 ? p5 2 /ta1 out /rtp0 2 ? p5 1 /ta0 in /rtp0 1 ? p5 0 /ta0 out /rtp0 0 ? p4 7 /cs 3 ? p4 6 /cs 2 ? p4 5 /cs 1 ? p4 4 /cs 0 ? p4 3 /hold ? p4 0 /ale ? 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 p4 2 /hlda ? p4 1 / 1 ? p6 5 /tb0 in ? p6 6 /tb1 in ? p6 7 /tb2 in ? p7 0 /an 0 ? ? p3 0 /rdy ? p3 1 /rd ? p3 2 /blw ? p3 3 /bhw byte v cont reset md0 v ss ? p2 5 /d 13 ? p2 4 /d 12 ? p2 6 /d 14 x in x out v cc ? p2 7 /d 15 ? p2 3 /d 11 ? p2 2 /d 10 ? p2 1 /d 9 ? p2 0 /d 8 ? p1 7 /d 7 /la 7 ? p1 6 /d 6 /la 6 ? p1 5 /d 5 /la 5 ? p1 0 /d 0 /la 0 ? p1 1 /d 1 /la 1 ? p1 2 /d 2 /la 2 v ss ? p10 5 /a 5 ? p10 4 /a 4 ? p10 7 /a 7 ? p10 6 /a 6 ? p11 0 /a 8 ? p11 2 /a 10 ? p11 1 /a 9 ? p11 3 /a 11 ? p11 5 /a 13 ? p11 4 /a 12 ? p11 6 /a 14 ? p0 0 /a 16 ? p11 7 /a 15 ? p0 1 /a 17 ? p0 2 /a 18 ? p0 4 /a 20 ? p0 3 /a 19 ? p0 5 /a 21 ? p0 7 /a 23 md1 ? p0 6 /a 22 ? p1 4 /d 4 /la 4 ? p1 3 /d 3 /la 3 p10 0 /a 0 ? p8 7 /t x d 1 ? p8 6 /r x d 1 ? p8 5 /cts 1 /clk 1 ? p8 4 /cts 1 /rts 1 /int 4 ? p8 3 /t x d 0 ? p10 3 /a 3 ? p10 2 /a 2 ? p10 1 /a 1 ? p8 2 /r x d 0 ? v cc av cc v ref av ss v ss p7 7 /an 7 /ad trg /da 1 /(int 2 ) ? p7 6 /an 6 /da 0 ? p7 5 /an 5 /(int 4 ) ? p7 4 /an 4 /(int 3 ) ? p7 3 /an 3 ? p7 2 /an 2 ? p7 1 /an 1 ? p8 0 /cts 0 /rts 0 /da 2 /int 3 ? nmi p8 1 /cts 0 /clk 0 ? m37902fcchp m37902fgchp m37902fjchp p5 7 /ta3 in /rtp1 3 /ki 3 ? p5 6 /ta3 out /rtp1 2 /ki 2 ?
3 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers block diagram data bank register dt (8) program counter pc (16) incrementer/decrementer (24) program bank register pg (8) input buffer register ib (16) direct page register dpr0 (16) stack pointer s (16) index register y (16) index register x (16) arithmetic logic unit (16) accumulator b (16) accumulator a (16) instruction register (8) central processing unit (cpu) incrementer (24) program address register pa (24) data address register da (24) bus interface unit (biu) reset md1 reference voltage input v ref (0v) av ss avcc vcc external data bus width select input byte clock generating circuit clock input x in v cont x out data buffer dq 0 (8) instruction queue buffer q 0 (8) data bus (odd) address bus a-d converter (10) uart1 (9) uart0 (9) watchdog timer timer tb1 (16) timer tb2 (16) timer tb0 (16) d-a 1 converter (8) d-a 2 converter (8) timer ta1 (16) timer ta2 (16) timer ta3 (16) timer ta4 (16) timer ta0 (16) ram (note) p8(8) input/output port p8 p7(8) input/output port p7 input/output port p4 p4(8) p10(8) input/output port p10 p6(8) input/output port p6 p5(8) input/output port p5 p11(8) input/output port p11 p1(8) input/output port p1 p2(8) input/output port p2 p3(4) input/output port p3 p0(8) input/output port p0 md0 (0v) vss processor status register ps (11) nmi flash memory (note) d-a 0 converter (8) data bus (even) data buffer dq 1 (8) data buffer dq 2 (8) data buffer dq 3 (8) instruction queue buffer q 1 (8) instruction queue buffer q 2 (8) instruction queue buffer q 3 (8) instruction queue buffer q 4 (8) instruction queue buffer q 5 (8) instruction queue buffer q 6 (8) instruction queue buffer q 7 (8) instruction queue buffer q 8 (8) instruction queue buffer q 9 (8) direct page register dpr1 (16) direct page register dpr2 (16) direct page register dpr3 (16) clock output reset input note: flash memory ram m37902fcchp 120 kbytes 4096 bytes m37902fgchp 248 kbytes 6144 bytes m37902fjchp 498 kbytes 12288 bytes
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 4 203 38 ns (the fastest instruction at f(f sys ) = 26 mhz) 26 mhz (max.) 26 mhz (max.) (note) (note) 16 kbytes 8-bit ? 10 4-bit ? 1 16-bit ? 5 16-bit ? 3 (uart or clock synchronous serial i/o) ? 2 10-bit successive approximation method ? 1 (8 channels) 8-bit ? 3 12-bit ? 1 chip select area ? 4 (cs 0 cs 3 ). a bus cycle type and bus width can be set for each chip select area. 4 bits ? 2 channels; or 6 bits ? 1 channel + 2 bits ? 1 channel 5 external types, 13 internal types. each interrupt can be set to a priority level within the range of 0 7 by software. 1 external type, 3 internal types. built-in (externally connected to a ceramic resonator or quartz crystal resonator). the following multiplication methods are available: double, triple, and quadruple. 5 v0.5 v 150 mw (at f(f sys ) = 26 mhz, typ., pll frequency multiplier stopped) 5 v 5 ma up to 16 mbytes. note that bank ff 16 is a reserved area. 20 to 85 c cmos high-performance silicon gate process 100-pin plastic molded qfp functions (microcomputer mode) functions parameter number of basic machine instructions instruction execution time external clock input frequency f(x in ) system clock frequency f(f sys ) memory size programmable input/output ports multi-functional timers serial i/o a-d converter d-a converter watchdog timer chip-select wait control real-time output interrupts clock generating circuit pll frequency multiplier input/output withstand voltage output current flash memory (user rom area) ram flash memory (boot rom area) p0 p2, p4 p8, p10, p11 p3 ta0 ta4 tb0 tb2 uart0 and uart1 power supply voltage power dissipation ports input/output characteristics memory expansion operating ambient temperature range device structure package maskable interrups non-maskable interrups flash memory m37902fcchp 120 kbytes (user rom area) m37902fgchp 248 kbytes m37902fjchp 498 kbytes ram m37902fcchp 4096 bytes m37902fgchp 6144 bytes m37902fjchp 12288 bytes note:
5 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers user rom area boot rom area flash memory parallel i/o mode flash memory serial i/o mode flash memory cpu reprogramming mode flash memory parallel i/o mode flash memory serial i/o mode flash memory cpu reprogramming mode power supply voltage programming/erase voltage flash memory mode block division for erasure programming method erase method programming/erase control data protection method number of commands maximum number of reprograms 5 v0.5 v (in the flash memory parallel i/o mode, 3.3 v0.3 v) 5 v0.5 v (in the flash memory parallel i/o mode, 3.3 v0.3 v) 3 modes: parallel i/o, serial i/o, and cpu reprogramming modes (note 1) 1 block (16 kbytes ? 1) (note 2) programmed per page (in a unit of 256 kbytes) user rom area + boot rom area user rom area user rom area total erase/block erase user rom area + boot rom area user rom area user rom area programming/erase control by software commands protected per block, by using a lock bit. 8 commands 100 functions (flash memory mode) functions parameter 2: on shipment, our reprogramming control firmware for the flash memory serial i/o mode has been stored into the boot rom area. note that the boot rom area can be erased/programmed only in the flash memory parallel i/o mode. user rom area m37902fcchp 5 blocks (8 kbytes ? 3, 32 kbytes ? 1, 64 kbytes ? 1), total 120 kbytes m37902fgchp 7 blocks (8 kbytes ? 3, 32 kbytes ? 1, 64 kbytes ? 3), total 248 kbytes m37902fjchp 11 blocks (2 kbytes ? 1, 8 kbytes ? 2, 32 kbytes ? 1, 64 kbytes ? 7), total 498 kbytes notes 1:
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 6 vcc, vss md0 md1 reset x in x out byte v cont avcc, avss v ref p0 0 p0 7 p1 0 p1 7 p2 0 p2 7 p3 0 p3 3 p4 0 p4 7 power supply input md0 md1 reset input clock input clock output external data bus width select input filter circuit connection analog power supply input reference voltage input i/o port p0 i/o port p1 i/o port p2 i/o port p3 i/o port p4 input input input input output input input i/o i/o i/o i/o i/o apply 5 v0.5 v to vcc, and 0 v to vss. this pin controls the processor mode. connect this pin to v ss for the single-chip mode or memory expansion mode, and v cc for the microprocessor mode. connect this pin to vss. the microcomputer is reset when l level is applied to this pin. these are input and output pins of the internal clock generating circuit. connect a ceramic or quartz- crystal resonator between the x in and x out pins. when an external clock is used, the clock source should be connected to the x in pin, and the x out pin should be left open. this pin determines whether the external data bus has an 8-bit width or 16-bit width for the memory expansion mode or microprocessor mode. the width is 16 bits when l signal is input, and 8 bits when h signal is input. when byte = vss level, by the register setting, the external data bus for each of areas cs 1 to cs 3 can have a width of 8 bits. when using the pll frequency multiplier, connect this pin to the filter circuit. when not using, this pin should be left open. power supply input pins for the a-d converter and the d-a converter. connect avcc to vcc, and avss to vss externally. this is the reference voltage input pin for the a-d converter and the d-a converter. in single-chip mode port p0 is an 8-bit i/o port. this port has an i/o direction register, and each pin can be programmed for input or output. these pins enter the input mode at reset. in memory expansion and microprocessor modes address (a 16 a 23 ) is output. these pins also function as i/o port pins according to the register setting. in single-chip mode these pins have the same functions as port p0. in memory expansion and microprocessor modes the low-order 8 bits of data (d 0 d 7 ) are input/output. when the external data bus has an 8-bit width, address (la 0 la 7 ) output and data (d 0 d 7 ) input/output can be performed with the time-sharing method, according to the register setting. in single-chip mode or when 8-bit external data bus is used in memory expansion mode and microprocessor mode these pins have the same functions as port p0. when the 16-bit external data bus is used in memory expansion or microproce- ssor mode the high-order 8 bits of data (d 8 d 15 ) are input or output. in single-chip mode these pins have the same functions as port p0. in memory expansion mode p3 0 functions as an i/o port pin; and p3 1 , p3 2 , and p3 3 function as the output pins of rd, blw, bhw, respectively. p3 0 also functions as an output pin of rdy according to the register setting. when the external data bus has a width of 8 bits, the bhw pin functions as an i/o port pin (p3 3 ). in microprocessor mode p3 0 functions as an input pin of rdy; and p3 1 ,p3 2 , p3 3 function as the output pins of rd, blw, bhw, respectively. p3 0 also functions as an i/o port pin accord- ing to the register setting. when the external data bus has a width of 8 bits, the bhw pin functions as an i/o port pin (p3 3 ). in single-chip mode these pins have the same functions as port p0. in memory expansion mode p4 0 p4 7 function as i/o port pins. according to the register setting, these pins function as output pins or input pins of ale, 1 , hlda, hold, cs 0 cs 3 , respec- tively. in microprocessor mode p4 0 p4 4 function as output or input pins of ale, 1 , hlda, hold, cs 0 , and p4 5 p4 7 as i/o port pins, respectively. according to the register setting, p4 0 p4 3 also function as i/o port pins, and p4 5 p4 7 as output pins of cs 1 cs 3 . pin description (microcomputer mode) functions input/ output name pin
7 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers i/o i/o i/o i/o i/o i/o input functions input/ output name pin p5 0 p5 7 p6 0 p6 7 p7 0 p7 7 p8 0 p8 7 p10 0 p10 7 p11 0 p11 7 nmi in addition to having the same functions as port p0 in the single-chip mode, these pins also function as i/o pins for timers a0 a3, output pins for the real-time output, and input pins for the key-input interrupt. in addition to having the same functions as port p0 in the single-chip mode, these pins also function as i/o pins for timer a4, input pins for external interrupt inputs ____ ____ int 0 int 2 , and input pins for timers b0 b2. in addition to having the same functions as port p0 in the single-chip mode, these pins also function as input pins for the a-d converter, output pins for the d-a converter, and input pins for int 2 , int 3 , and int 4 . in addition to having the same functions as port p0 in the single-chip mode, these pins also function as i/o pins for uart0, uart1, output pins for d-a converter, and input pins for int 3 and int 4 . in single-chip mode these pins have the same functions as port p0. in memory expansion and microprocessor modes address (a 0 a 7 ) is output. in single-chip mode these pins have the same functions as port p0. in memory expansion and microprocessor modes address (a 8 a 15 ) is output. also, these pins function as i/o port pins according to the register setting. this pin is for a non-maskable interrupt. i/o port p5 i/o port p6 i/o port p7 i/o port p8 i/o port p10 i/o port p11 non-maskable interrupt
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 8 pin description (flash memory serial i/o mode) v cc , v ss md0 md1 _____ reset x in x out byte v cont avcc, avss v ref p0 0 p0 7 p1 0 p1 7 p2 0 p2 7 p3 0 p3 3 p4 0, p4 4 p4 7 p4 1 p4 2 p4 3 p5 0 p5 7 p6 0 p6 7 p7 0 p7 7 p8 0 p8 7 p10 0 p10 7 p11 0 p11 7 nmi pin power supply input md0 md1 reset input clock input clock output byte filter circuit connection analog supply input reference voltage input input port p0 input port p1 input port p2 input port p3 input port p4 sclk input sda i/o busy output input port p5 input port p6 input port p7 input port p8 input port p10 input port p11 non-maskable interrupt name input input input input output input input input input input input input input i/o output input input input input input input input input /output functions apply 5 v 0.5 v to vcc, and 0 v to vss. connect this pin to vss. connect this pin to vss via a resistor of 10 k ? to 100 k ? . the reset input pin. connect a ceramic resonator between the x in and x out pins, or input an external clock from the x in pin with the x out pin left open. connect this pin to vcc or vss. (this is not used in the flash memory serial i/o mode.) connect this pin to the filter circuit, or leave this pin open. (this is not used in the flash memory serial i/o mode.) connect avcc to vcc, and avss to vss. input an arbitrary level within the range of v ss v cc . (this is not used in the flash memory serial i/o mode.) input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) this is an input pin for a serial clock. this is an i/o pin for serial data. connect this pin to v cc via a resistor (about 1 k ? ). this is an output pin for the busy signal. input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) input h , or leave this pin open.
9 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers basic function blocks these microcomputers contain the following devices on the single chip: the flash memory, ram, cpu, bus interface unit, and periph- eral devices such as the interrupt control circuit, timers, serial i/o, a-d converter, d-a converter, i/o ports, clock generating circuit, etc. memory figures 1 to 3 show the memory maps. the address space is 16 mbytes from addresses 0 16 to ffffff 16 . the address space is di- vided into 64-kbyte units called banks. the banks are numbered from 0 16 to ff 16 . bank ff 16 is a reserved area for the development support tool. therefore, do not use bank ff 16 . internal flash memory and internal ram are assigned as shown in figures 1 to 3. addresses ffc0 16 to ffff 16 contain the reset and the interrupt vector addresses, and the interrupt vectors are stored there. for details, refer to the section on interrupts. assigned to addresses 0 16 to ff 16 are peripheral devices such as i/o ports, a-d converter, d-a converter, uart, timers, interrupt con- trol registers, etc. figures 7 and 8 show the location of sfrs. for the flash memory in the boot rom area, refer to the section on the flash memory mode. fig. 1 memory map of m37902fcchp (single-chip mode) int 4 a-d conversion reserved area reserved area address matching detect reserved area reserved area reserved area reserved area reserved area uart1 transmit uart1 receive uart0 transmit uart0 receive timer b2 timer b1 timer b0 interrupt vector table timer a4 timer a3 timer a2 timer a1 timer a0 watchdog timer brk instruction zero divide int 3 int 2 int 1 int 0 nmi reset dbc 000000 16 bank 0 16 ffffff 16 fe0000 16 00ffff 16 010000 16 01ffff 16 bank fe 16 000000 16 000800 16 0000ff 16 00fffe 16 00ffc0 16 internal ram 4096 bytes internal flash memory 120 kbytes (user rom area) peripheral devices control registers 001fff 16 002000 16 feffff 16 ff0000 16 0017ff 16 001800 16 00ffff 16 00ffc0 16 bank 1 16 bank ff 16 reserved area for development support tool
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 10 fig. 3 memory map of m37902fjchp (single-chip mode) reserved area for development support tool int 4 a-d conversion reserved area reserved area address matching detect reserved area reserved area reserved area reserved area reserved area uart1 transmit uart1 receive uart0 transmit uart0 receive timer b2 timer b1 timer b0 interrupt vector table timer a4 timer a3 timer a2 timer a1 timer a0 watchdog timer brk instruction zero divide int 3 int 2 int 1 int 0 nmi reset dbc 000000 16 bank 0 16 ffffff 16 fe0000 16 00ffff 16 020000 16 02ffff 16 bank fe 16 000000 16 000800 16 0000ff 16 00fffe 16 00ffc0 16 internal ram 12288 bytes internal flash memory 498 kbytes (user rom area) peripheral devices control registers 0037ff 16 003800 16 feffff 16 ff0000 16 00ffff 16 00ffc0 16 bank 2 16 010000 16 01ffff 16 bank 1 16 030000 16 bank 3 16 03ffff 16 050000 16 05ffff 16 bank 5 16 040000 16 04ffff 16 bank 4 16 060000 16 bank 6 16 06ffff 16 070000 16 07ffff 16 bank 7 16 bank ff 16 fig. 2 memory map of m37902fgchp (single-chip mode) int 4 a-d conversion reserved area reserved area address matching detect reserved area reserved area reserved area reserved area reserved area uart1 transmit uart1 receive uart0 transmit uart0 receive timer b2 timer b1 timer b0 interrupt vector table timer a4 timer a3 timer a2 timer a1 timer a0 watchdog timer brk instruction zero divide int 3 int 2 int 1 int 0 nmi reset dbc 000000 16 bank 0 16 ffffff 16 fe0000 16 00ffff 16 010000 16 01ffff 16 bank fe 16 000000 16 000800 16 0000ff 16 00fffe 16 00ffc0 16 internal ram 6144 bytes internal flash memory 248 kbytes (user rom area) peripheral devices control registers 001fff 16 002000 16 feffff 16 ff0000 16 00ffff 16 00ffc0 16 bank 1 16 bank ff 16 020000 16 02ffff 16 bank 2 16 030000 16 03ffff 16 bank 3 16 reserved area for development support tool
11 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers fig. 7 location of sfrs (1) 000000 16 000001 16 000002 16 000003 16 000004 16 000005 16 000006 16 000007 16 000008 16 000009 16 00000a 16 00000b 16 00000c 16 00000d 16 00000e 16 00000f 16 000010 16 000011 16 000012 16 000013 16 000014 16 000015 16 000016 16 000017 16 000018 16 000019 16 00001a 16 00001b 16 00001c 16 00001d 16 00001e 16 00001f 16 000020 16 000021 16 000022 16 000023 16 000024 16 000025 16 000026 16 000027 16 000028 16 000029 16 00002a 16 00002b 16 00002c 16 00002d 16 00002e 16 00002f 16 000030 16 000031 16 000032 16 000033 16 000034 16 000035 16 000036 16 000037 16 000038 16 000039 16 00003a 16 00003b 16 00003c 16 00003d 16 00003e 16 00003f 16 port p2 register port p3 register port p1 direction register port p0 direction register port p1 register port p0 register port p2 direction register port p3 direction register port p4 register port p5 register port p4 direction register port p5 direction register port p6 register port p7 register port p6 direction register port p7 direction register port p8 register port p8 direction register port p10 register port p11 register port p10 direction register port p11 direction register a-d control register 0 a-d control register 1 a-d register 0 a-d register 1 a-d register 2 a-d register 3 a-d register 4 a-d register 5 a-d register 6 a-d register 7 uart0 transmit/receive mode register uart0 baud rate register (brg0) uart0 transmit buffer register uart0 transmit/receive control register 1 uart0 receive buffer register uart1 transmit/receive mode register uart1 baud rate register (brg1) uart1 transmit buffer register uart1 transmit/receive control register 0 uart1 transmit/receive control register 1 uart1 receive buffer register address (hexadecimal notation) 000040 16 000041 16 000042 16 000043 16 000044 16 000045 16 000046 16 000047 16 000048 16 000049 16 00004a 16 00004b 16 00004c 16 00004d 16 00004e 16 00004f 16 000050 16 000051 16 000052 16 000053 16 000054 16 000055 16 000056 16 000057 16 000058 16 000059 16 00005a 16 00005b 16 00005c 16 00005d 16 00005e 16 00005f 16 000060 16 000061 16 000062 16 000063 16 000064 16 000065 16 000066 16 000067 16 000068 16 000069 16 00006a 16 00006b 16 00006c 16 00006d 16 00006e 16 00006f 16 000070 16 000071 16 000072 16 000073 16 000074 16 000075 16 000076 16 000077 16 000078 16 000079 16 00007a 16 00007b 16 00007c 16 00007d 16 00007e 16 00007f 16 address (hexadecimal notation) count start register one-shot start register timer a clock division select register timer a0 register timer a1 register timer a2 register timer a3 register timer a4 register timer b0 register timer b1 register timer b2 register timer a1 mode register timer a0 mode register timer a2 mode register timer a3 mode register timer a4 mode register timer b0 mode register timer b1 mode register timer b2 mode register processor mode register 1 watchdog timer register particular function select register 0 particular function select register 1 debug control register 0 int 3 interrupt control register uart0 transmit interrupt control register uart1 receive interrupt control register timer a0 interrupt control register timer a1 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b0 interrupt control register timer b2 interrupt control register int 1 interrupt control register watchdog timer frequency select register debug control register 1 int 4 interrupt control register uart1 transmit interrupt control register timer a2 interrupt control register timer b1 interrupt control register int 2 interrupt control register address comparison register 0 address comparison register 1 particular function select register 2 reserved area (note) note: do not write to this address. uart0 transmit/receive control register 0 up-down register processor mode register 0 a-d conversion interrupt control register uart0 receive interrupt control register int 0 interrupt control register reserved area (note) reserved area (note)
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 12 fig. 8 location of sfrs (2) 0000c0 16 0000c1 16 0000c2 16 0000c3 16 0000c4 16 0000c5 16 0000c6 16 0000c7 16 0000c8 16 0000c9 16 0000ca 16 0000cb 16 0000cc 16 0000cd 16 0000ce 16 0000cf 16 0000d0 16 0000d1 16 0000d2 16 0000d3 16 0000d4 16 0000d5 16 0000d6 16 0000d7 16 0000d8 16 0000d9 16 0000da 16 0000db 16 0000dc 16 0000dd 16 0000de 16 0000df 16 0000e0 16 0000e1 16 0000e2 16 0000e3 16 0000e4 16 0000e5 16 0000e6 16 0000e7 16 0000e8 16 0000e9 16 0000ea 16 0000eb 16 0000ec 16 0000ed 16 0000ee 16 0000ef 16 0000f0 16 0000f1 16 0000f2 16 0000f3 16 0000f4 16 0000f5 16 0000f6 16 0000f7 16 0000f8 16 0000f9 16 0000fa 16 0000fb 16 0000fc 16 0000fd 16 0000fe 16 0000ff 16 0000a0 16 0000a1 16 0000a2 16 0000a3 16 0000a4 16 0000a5 16 0000a6 16 0000a7 16 0000a8 16 0000a9 16 0000aa 16 0000ab 16 0000ac 16 0000ad 16 0000ae 16 0000af 16 0000b0 16 0000b1 16 0000b2 16 0000b3 16 0000b4 16 0000b5 16 0000b6 16 0000b7 16 0000b8 16 0000b9 16 0000ba 16 0000bb 16 0000bc 16 0000bd 16 0000be 16 0000bf 16 real-time output control register pulse output data register 0 pulse output data register 1 serial i/o pin control register 000080 16 000081 16 000082 16 000083 16 000084 16 000085 16 000086 16 000087 16 000088 16 000089 16 00008a 16 00008b 16 00008c 16 00008d 16 00008e 16 00008f 16 000090 16 000091 16 000092 16 000093 16 000094 16 000095 16 000096 16 000097 16 000098 16 000099 16 00009a 16 00009b 16 00009c 16 00009d 16 00009e 16 00009f 16 address (hexadecimal notation) cs 0 control register l cs 0 control register h cs 1 control register l cs 1 control register h cs 2 control register l cs 2 control register h cs 3 control register l cs 3 control register h area cs 0 start address register area cs 1 start address register area cs 2 start address register area cs 3 start address register reserved area (note) reserved area (note) port function control register external interrupt input control register external interrupt input read-out register d-a control register d-a register 0 d-a register 1 d-a register 2 flash memory control register note: do not write to this address. clock control register reserved area (note) reserved area (note) reserved area (note) address (hexadecimal notation) reserved area (note) reserved area (note)
m37902fcchp, m37902fgchp, m37902fjchp 13 mitsubishi microcomputers shingle-chip 16-bit cmos microcomputer central processing unit (cpu) the cpu has 13 registers and is shown in figure 9. each of these registers is described below. accumulator a (a) accumulator a is the main register of the microcomputer. it consists of 16 bits and the low-order 8 bits can be used separately. data length flag m determines whether the register is used as 16-bit reg- ister or as 8-bit register. it is used as a 16-bit register when flag m is ??and as an 8-bit register when flag m is ?? flag m is a part of the processor status register (ps) which is described later. data operations such as calculations, data transfer, input/output, etc., are executed mainly through accumulator a. accumulator b (b) accumulator b has the same functions as accumulator a, but the use of accumulator b requires more instruction bytes and execution cycles than accumulator a. accumulator e accumulator e is a 32-bit register and consists of accumulator a (low-order 16 bits) and accumulator b (high-order 16 bits). it is used for 32-bit data processing. index register x (x) index register x consists of 16 bits and the low-order 8 bits can be used separately. index register length flag x determines whether the register is used as 16-bit register or as 8-bit register. it is used as a 16-bit register when flag x is ??and as an 8-bit register when flag x is ?? flag x is a part of the processor status register (ps) which is described later. in index addressing modes in which register x is used as the index register, the contents of this address are added to obtain the real ad- dress. index register x functions as a pointer register which indicates an address of data table in instructions mvp, mvn, rmpa (repeat multiply and accumulate). index register y (y) index register y consists of 16 bits and the low-order 8 bits can be used separately. the index register length flag x determines whether the register is used as 16-bit register or as 8-bit register. it is used as a 16-bit register when flag x is ??and as an 8-bit register when flag x is ?? flag x is a part of the processor status register (ps) which is described later. in index addressing modes in which register y is used as the index register, the contents of this address are added to obtain the real ad- dress. index register y functions as a pointer register which indicates an address of data table in instructions mvp, mvn, rmpa (repeat multiply and accumulate). 1570 1570 15 7 0 1570 15 0 15 0 15 0 15 7 0 00000 ipl 2 ipl 1 ipl 0 nvmxd i zc dpr0 to dpr3 pc s y h y l x h x l b h b l a h a l accumulator a accumulator b index register x index register y stack pointer s program counter pc direct page registers dpr0 to dpr3 processor status register ps carry flag zero flag interrupt disable flag decimal mode flag index register length flag data length flag overflow flag negative flag processor interrupt priority level ipl 70 70 pg program bank register pg data bank register dt dt 15 7 0 15 7 0 a h a l b h b l accumulator e 31 0 fig. 9 register structure
m37902fcchp, m37902fgchp, m37902fjchp mitsubishi microcomputers 14 shingle-chip 16-bit cmos microcomputer stack pointer (s) stack pointer (s) is a 16-bit register. it is used during a subroutine call or interrupts. it is also used during stack, stack pointer relative, or stack pointer relative indirect indexed y addressing mode. program counter (pc) program counter (pc) is a 16-bit counter that indicates the low-order 16 bits of the next program memory address to be executed. there is a bus interface unit between the program memory and the cpu, so that the program memory is accessed through bus interface unit. this is described later. program bank register (pg) program bank register is an 8-bit register that indicates the high-or- der 8 bits of the next program memory address to be executed. when a carry occurs by incrementing the contents of the program counter, the contents of the program bank register (pg) is increased by 1. also, when a carry or borrow occurs after adding or subtracting the offset value to or from the contents of the program counter (pc) using the branch instruction, the contents of the program bank regis- ter (pg) is increased or decreased by 1, so that programs can be written without worrying about bank boundaries. data bank register (dt) data bank register (dt) is an 8-bit register. with some addressing modes, the data bank register (dt) is used to specify a part of the memory address. the contents of data bank register (dt) is used as the high-order 8 bits of a 24-bit address. addressing modes that use the data bank register (dt) are direct indirect, direct indexed x indi- rect, direct indirect indexed y, absolute, absolute bit, absolute in- dexed x, absolute indexed y, absolute bit relative, and stack pointer relative indirect indexed y. direct page registers 0 to 3 (dpr0 to dpr3) the direct page register is a 16-bit register. an addressing mode of which name includes direct generates an address of data to be ac- cessed, regarding the contents of this register as the base address. the 7900 series has been expanded direct page registers up to 4 (dpr0 to dpr3), in comparison to the 7700 series which has the single direct page register. accordingly, the 7900 series s direct ad- dressing method which uses direct page registers differs from that of the 7700 series. however, the conventional direct addressing method, using only dpr0, is still be selectable, in order to make use of the 7700 series software property. for more details, refer to the section on the direct page. processor status register (ps) processor status register (ps) is an 11-bit register. it consists of flags to indicate the result of operation and cpu interrupt levels. branch operations can be performed by testing the flags c, z, v, and n. the details of each bit of the processor status register are described below. 1. carry flag (c) the carry flag contains the carry or borrow generated by the alu af- ter an arithmetic operation. this flag is also affected by shift and ro- tate instructions. this flag can be set and reset directly with the sec and clc instructions or with the sep and clp instructions. 2. zero flag (z) the zero flag is set if the result of an arithmetic operation or data transfer is zero and reset if it is not. this flag can be set and reset directly with the sep and clp instructions. 3. interrupt disable flag (i) when the interrupt disable flag is set to 1 , all interrupts except ___ watchdog timer, nmi, and software interrupt are disabled. this flag is set to 1 automatically when an interrupt is accepted. it can be set and reset directly with the sei and cli instructions or sep and clp instructions. 4. decimal mode flag (d) the decimal mode flag determines whether addition and subtraction are performed as binary or decimal. binary arithmetic is performed when this flag is 0 . if it is 1 , decimal arithmetic is performed with each word treated as 2- or 4- digit decimal. arithmetic operation is performed using four digits when data length flag m is 0 and with two digits when it is 1 . decimal adjust is automatically performed. (decimal operation is possible only with the adc and sbc instruc- tions.) this flag can be set and reset with the sep and clp instruc- tions.
m37902fcchp, m37902fgchp, m37902fjchp 15 mitsubishi microcomputers shingle-chip 16-bit cmos microcomputer 5. index register length flag (x) the index register length flag determines whether index register x and index register y are used as 16-bit registers or as 8-bit registers. the registers are used as 16-bit registers when flag x is 0 and as 8- bit registers when it is 1 . this flag can be set and reset with the sep and clp instructions. 6. data length flag (m) the data length flag determines whether the data length is 16-bit or 8-bit. the data length is 16 bits when flag m is 0 and 8 bits when it is 1 . this flag can be set and reset with the sem and clm instruc- tions or with the sep and clp instructions. 7. overflow flag (v) the overflow flag is valid when addition or subtraction is performed with a word treated as a signed binary number. if data length flag m is 0 , the overflow flag is set when the result of addition or subtrac- tion is outside the range between 32768 and +32767. if data length flag m is 1 , the overflow flag is set when the result of addition or subtraction is outside the range between 128 and +127. it is reset in all other cases. the overflow flag can also be set and reset directly with the sep, and clv or clp instructions. additionally, the overflow flag is set when a result of unsigned/signed division exceeds the length of the register where the result is to be stored; the flag is also set when the addition result is outside range of 2147483648 to +2147483647 in the rmpa operation. 8. negative flag (n) the negative flag is set when the result of arithmetic operation or data transfer is negative (if data length flag m is 0 , data s bit 15 is 1 . if data length flag m is 1 , data s bit 7 is 1 .) it is reset in all other cases. it can also be set and reset with the sep and clp instruc- tions. 9. processor interrupt priority level (ipl) the processor interrupt priority level (ipl) consists of 3 bits and de- termines the priority of processor interrupts from level 0 to level 7. interrupt is enabled when the interrupt priority of the device request- ing interrupt (set using the interrupt control register) is higher than the processor interrupt priority. when an interrupt is enabled, the cur- rent processor interrupt priority level is saved in a stack and the pro- cessor interrupt priority level is replaced by the interrupt priority level of the device requesting the interrupt. refer to the section on inter- rupts for more details. note: fix bits 11 to 15 of the processor status register (ps) to 0 .
m37902fcchp, m37902fgchp, m37902fjchp mitsubishi microcomputers 16 shingle-chip 16-bit cmos microcomputer bank in order to effectively use the integrated hardware on the chip, this cpu core uses an address generating method with a 24-bit address split into high-order 8 bits and low-order 16 bits. in other words, the 64 kbytes specified by the low-order 16 bits are one unit (referred to as bank ), and the address space is divided into 256 banks (0 16 to ff 16 ) specified by the high-order 8 bits. in the program area on the address space, the bank is specified by the program bank register (pg), and the address in the bank is specified by the program counter (pc). as for each bank boundary, when an overflow has occurred in pc, the contents of pg are incremented by 1. when a borrow has oc- curred in pc, the contents of pg are decremented by 1. under the normal conditions, therefore, programming without concern for the bank boundaries is possible. furthermore, as for the data area on the address space, the bank is specified by the data bank register (dt), and the address in the bank is specified by the operation result by using the various addressing modes (note). note: some addressing modes directly specify a bank. direct page the internal memory and control registers for internal peripheral de- vices, etc. are assigned to bank 0 16 (addresses 0 16 to ffff 16 ). the direct page and direct addressing modes have been provided for the effective access to bank 0 16 . in the 7900 series, two types of direct addressing modes are available: the conventional direct addressing mode which uses only dpr0, as in the 7700 series, and the ex- panded direct addressing mode, which uses up to 4 direct page reg- isters as selected by the user. the addressing mode is selected according to the contents of bit 1 of the processor mode register 1. this bit 1 is cleared to 0 at reset. (in other words, the conventional direct addressing mode is selected.) however, once this bit 1 has been set to 1 by software, this bit cannot be cleared to 0 again, except by reset. that is to say, when one of these two direct address- ing modes has been selected just after reset, the selected address- ing mode cannot be switched to another one while the program is running. conventional direct addressing mode the direct page area consists of 256-byte space. its bank address is 00 16 , and the base address of its low-order 16-bit address is speci- fied by the contents of the direct page register 0 (dpr0). in this con- ventional direct addressing modes, a value (1 byte) just after an instruction code is regarded as an offset value for the dpr0 con- tents, and the cpu accesses each address in the direct page area. expanded direct addressing mode the direct page area consists of four 64-byte spaces. their bank address is 00 16 , and the four base addresses of their low-order 16- bit addresses are respectively specified by the contents of four direct page registers. in this expanded direct addressing mode, a value (1 byte) just after an instruction code is regarded as follows: high-order 2 bits: regarded as a selection field for dpr0 to dpr3. low-order 6 bits: regarded as an offset value for the selected direct page register. then, the cpu accesses each address in each direct page area: refer to 7900 series software manual for details concerning the various addressing modes which use the direct page area. instruction set the cpu core of the 7900 series has an expanded instruction set based on the existing 7700/7751 series cpu core. in addition, its source code (mnemonic) has the complete upper compatibility with the 7700 series instruction set. for details concerning addressing modes and instruction set, refer to 7900 series software manual .
m37902fcchp, m37902fgchp, m37902fjchp 17 mitsubishi microcomputers shingle-chip 16-bit cmos microcomputer bus interface unit data transfer between the central processing unit (cpu) and inter- nal memory, internal peripheral devices, or external areas is always performed via the bus interface unit (biu), which is located between the cpu and the internal buses. figure 10 shows the biu and the bus structure. the cpu and biu are connected by a dedicated bus, and any transfer between the cpu and biu is controlled by this dedicated bus. on the other hand, data transfer between the biu and internal pe- ripheral devices uses the following internal common buses: 32-bit code bus, 16-bit data bus, 24-bit address bus, and control signals. the bus control method where the code bus and the data bus sepa- rate out (hereafter, this method is referred to as the separate code/ fig. 10 biu and bus structure internal code bus (cb 0 to cb 31 ) central processing unit (cpu) sfr : special function register ? the cpu bus, internal bus, and external bus separate out independently. external devices internal control signal cpu bus internal buses internal data bus (db 0 to db 15 ) internal memory internal peripheral devices (sfr) external bus a 0 to a 23 d 0 to d 7 (la 0 to la 7 ) d 8 to d 15 control signal bus interface unit (biu) bus conversion circuit internal address bus (ad 0 to ad 23 ) hold hold request hlda m37902 data bus method) is employed in order to improve data transfer ca- pabilities. as a result, the internal memory is connected to both the code bus and the data bus, and registers of all other internal periph- eral devices are connected only to the data bus. each width of external buses are as follows: a 24-bit address bus, 16-bit data bus. the external data bus transfers instruction codes and data. when the code or data access occurs for the external, the external access is performed via the bus conversion circuit. for details of the connection with the external devices, refer to the section on the processor modes and chip select wait controller de- scribed later.
m37902fcchp, m37902fgchp, m37902fjchp mitsubishi microcomputers 18 shingle-chip 16-bit cmos microcomputer name program address register instruction queue buffer data address register data buffer biu structure the biu consists of four registers shown in figure 11. table 1 lists the functions of each register. table 1. functions of each register fig.11 register structure of biu functions indicates a storage address for an instruction to be next taken into an instruction queue buffer. temporarily stores an instruction which has been taken from a memory. consists of 10 bytes. indicates an address where data will be next read from or written to. temporarily stores data which has been read from internal memory, internal peripheral devices, and external areas by the biu; or temporarily stores data which is to be written to internal memory, internal peripheral devices, and external areas by the cpu. consists of 32 bits. pa q0 q9 da dq b23 b0 b7 b0 b23 b0 b31 b0 program address register instruction queue buffer data address register data buffer
m37902fcchp, m37902fgchp, m37902fjchp 19 mitsubishi microcomputers shingle-chip 16-bit cmos microcomputer x 0 0 ad 1 (a 1 ) even address 4-byte boundary 8-byte boundary biu functions (1) instruction prefetch the biu has ten instruction queue buffers; each buffer consists of 1 byte. when there is an opening in the bus and the instruction queue buffer, an instruction code is read from the program memory (in other words, the memory where a program is stored) and prefetched into an instruction queue buffer. the prefetched instruction code is trans- ferred from the biu to the cpu, in response to a request from the cpu, via a dedicated bus. when a branch occurs as a result of a branch instruction (jmp, bra, etc.), subroutine call, or interrupt, the contents of the instruction queue buffer are initialized and the biu reads a new instruction from the branch destination address. note that the operations of the biu instruction prefetch also differ de- pending on the store addresses for instructions. the store addresses for instructions to be prefetched are categorized as listed in table 2. (2) data read operation when executing an instruction for reading data from the internal memory, internal peripheral devices, or external areas, at first, the cpu informs the bius data address register of the address where the data has been located. next, the biu reads the above data from the specified address, passes it to the data buffer, and then, transfers it to the cpu. (3) data write operation when executing an instruction for writing data into the internal memory, internal peripheral devices, or external area, at first, the cpu informs the bius data address register of the address where the data has been located. next, the biu passes the above data to the data buffer register, and then, writes it into the specified address. (4) bus cycle in order for the biu to execute the above operations (1) through (3), the 24-bit address bus, 32-bit code bus, 16-bit data bus and internal control signals must be appropriately controlled during data transfer between the biu and internal memory, internal peripheral devices, external areas. this operation is called ?us cycle? the bus cycle is affected by the following conditions at instruction prefetch and data access. [instruction prefetch] ?whether the address area locates in the internal area or the ex- ternal area. ?when the address area locates in the external area ? whether the external bus width = 16 bits or 8 bits: (a) when the external bus width = 16 bits: whether the start address for access locates at a 4- byte boundary or at an 8-byte boundary. (b) when the external bus width = 8 bits: whether the start address for access locates at an even address, a 4-byte boundary or at the 8-byte bound ary. ? whether the prefetch operation is generated by a branch, or not. ? number of waits ? whether the burst rom access is specified or not. table 2. store addresses for instructions to be prefetched low-order 3 bits of store address for instruction ad 2 (a 2 ) x x 0 0 0 0 ad 0 (a 0 ) [data access] ?whether the address area locates in the internal area or the ex- ternal area. ?length of data to be transferred: byte, word, double word ?when the address area locates in the external area: ? whether the external bus width = 16 bits or 8 bits: ? number of waits the biu controls the bus cycle depending on the above conditions. figures 12 to 16 show the bus cycle waveform examples for instruc- tion prefetch and data access. x: 0 or 1
m37902fcchp, m37902fgchp, m37902fjchp mitsubishi microcomputers 20 shingle-chip 16-bit cmos microcomputer access to internal area access to external area when address locates at 4-byte boundary or when branched: double consecutive access when branched or at instruction prefetch when external data bus width = 16 bits when external data bus width = 8 bits biu internal address bus internal code bus cb 0 to cb 31 code 1 a 0 to a 23 d 0 to d 7 d 8 to d 15 ale rd blw bhw d 0 to d 7 d 0 to d 7 d 8 to d 15 d 8 to d 15 address address + 2 when address of instruction to be prefetched locates at 8-byte boundary: quadruple consecutive access 1 a 0 to a 23 d 0 to d 7 d 8 to d 15 ale rd blw bhw d 0 to d 7 d 0 to d 7 d 0 to d 7 d 0 to d 7 d 8 to d 15 d 8 to d 15 d 8 to d 15 d 8 to d 15 address address + 2 address + 4 address + 6 when address is even address or when branched: double consecutive access 1 a 0 to a 23 d 0 to d 7 ale rd blw bhw d 0 to d 7 d 0 to d 7 address address + 1 when address of instruction to be prefetched locates at 4-byte boundary or 8-byte boundary: quadruple consecutive access 1 a 0 to a 23 d 0 to d 7 ale rd blw bhw d 0 to d 7 d 0 to d 7 d 0 to d 7 d 0 to d 7 address address + 1 address + 2 address + 3 address fig. 12 bus cycle waveform example for instruction prefetch
m37902fcchp, m37902fgchp, m37902fjchp 21 mitsubishi microcomputers shingle-chip 16-bit cmos microcomputer access to internal area 8-bit data read 8-bit data written 16-bit data read 16-bit data written access starting from even address access starting from odd address biu internal address bus internal data bus db 0 to db 7 db 8 to db 15 d 0 to d 7 address biu internal address bus internal data bus db 0 to db 7 db 8 to db 15 biu internal address bus internal data bus db 0 to db 7 db 8 to db 15 d 0 to d 7 address biu internal address bus internal data bus db 0 to db 7 db 8 to db 15 address biu internal address bus internal data bus db 0 to db 7 db 8 to db 15 d 0 to d 7 address 1 a 0 to a 23 d 0 to d 7 d 8 to d 15 d 0 to d 7 address d 8 to d 15 biu internal address bus internal data bus db 0 to db 7 db 8 to db 15 d 8 to d 15 d 0 to d 7 d 8 to d 15 d 8 to d 15 1 a 0 to a 23 d 0 to d 7 d 8 to d 15 address address + 1 d 8 to d 15 d 0 to d 7 d 8 to d 15 invalid invalid invalid invalid address address + 1 address 32-bit data read 32-bit data written biu internal address bus internal data bus db 0 to db 7 db 8 to db 15 address address + 2 d 8 to d 15 d 0 to d 7 d 0 to d 7 d 8 to d 15 biu internal address bus internal data bus db 0 to db 7 db 8 to db 15 address address + 1 address + 3 d 8 to d 15 d 0 to d 7 d 8 to d 15 d 0 to d 7 biu internal data bus db 0 to db 7 db 8 to db 15 d 8 to d 15 d 0 to d 7 d 8 to d 15 d 0 to d 7 biu internal address bus internal data bus db 0 to db 7 db 8 to db 15 d 8 to d 15 d 0 to d 7 d 0 to d 7 d 8 to d 15 invalid invalid address address + 2 address address + 1 address + 3 internal address bus fig. 13 bus cycle waveform example for data access (access to internal area)
m37902fcchp, m37902fgchp, m37902fjchp mitsubishi microcomputers 22 shingle-chip 16-bit cmos microcomputer external data bus width = 16 bits 8-bit data read 8-bit data written 16-bit data read 16-bit data written access starting from even address access starting from odd address 1 a 0 to a 23 d 0 to d 7 d 8 to d 15 ale rd blw bhw d 0 to d 7 address 1 a 0 to a 23 d 0 to d 7 d 8 to d 15 ale rd blw bhw address 1 a 0 to a 23 d 0 to d 7 d 8 to d 15 ale rd blw bhw d 0 to d 7 address 1 a 0 to a 23 d 0 to d 7 d 8 to d 15 ale rd blw bhw address 1 a 0 to a 23 d 0 to d 7 d 8 to d 15 ale rd blw bhw d 7 to d 0 address 1 a 0 to a 23 d 0 to d 7 d 8 to d 15 ale rd blw bhw d 0 to d 7 address d 8 to d 15 1 a 0 to a 23 d 0 to d 7 d 8 to d 15 ale rd blw bhw address address + 1 d 8 to d 15 d 0 to d 7 d 8 to d 15 d 8 to d 15 1 a 0 to a 23 d 0 to d 7 d 8 to d 15 ale rd blw bhw address address + 1 d 8 to d 15 d 0 to d 7 d 8 to d 15 invalid invalid invalid invalid fig. 14 bus cycle waveform example for data access (access to external area) (1)
m37902fcchp, m37902fgchp, m37902fjchp 23 mitsubishi microcomputers shingle-chip 16-bit cmos microcomputer fig. 15 bus cycle waveform example for data access (access to external area) (2) external data bus width = 16 bits 32-bit data read 32-bit data written access starting from even address access starting from odd address 1 a 0 to a 23 d 0 to d 7 d 8 to d 15 ale rd blw bhw address address + 2 d 8 to d 15 d 0 to d 7 d 0 to d 7 d 8 to d 15 1 a 0 to a 23 d 0 to d 7 d 8 to d 15 ale rd blw bhw address address + 1 address + 3 d 8 to d 15 d 0 to d 7 d 8 to d 15 d 0 to d 7 1 a 0 to a 23 d 0 to d 7 d 8 to d 15 ale rd blw bhw address address + 1 address + 3 d 8 to d 15 d 0 to d 7 d 8 to d 15 d 0 to d 7 1 a 0 to a 23 d 0 to d 7 d 8 to d 15 ale rd blw bhw address address + 2 d 8 to d 15 d 0 to d 7 d 0 to d 7 d 8 to d 15 invalid invalid
m37902fcchp, m37902fgchp, m37902fjchp mitsubishi microcomputers 24 shingle-chip 16-bit cmos microcomputer fig. 16 bus cycle waveform example for data access (access to external area) (3) note : when the voltage level at pin byte = l , functions as pins d 8 to d 15 are valid. however, when 8-bit width is selected as the external bus width by the chip select wait controller, the functions as pins d 8 to d 15 and bhw become invalid. (d 8 to d 15 = floating, bhw = h output.) when the voltage level at pin byte = h , these pins function as programmable i/o port (p2, p3 3 ) pins. external data bus width = 8 bits 32/16/ 8-bit data read 32/16/ 8-bit data written access starting from even or odd address 1 a 0 to a 23 d 0 to d 7 d 8 to d 15 (note) (note) ale rd blw bhw address address + 1 address + 2 address + 3 d 0 to d 7 d 0 to d 7 d 0 to d 7 d 0 to d 7 1 a 0 to a 23 d 0 to d 7 d 8 to d 15 (note) (note) ale rd blw bhw address address + 1 address + 2 address + 3 d 0 to d 7 d 0 to d 7 d 0 to d 7 d 0 to d 7 8-bit data access 16-bit data access 32-bit data access 8-bit data access 16-bit data access 32-bit data access
m37902fcchp, m37902fgchp, m37902fjchp 25 mitsubishi microcomputers shingle-chip 16-bit cmos microcomputer fig. 17 bus cycle waveform at access to internal area 1 bus cycle = 3 (note) (internal rom bus cycle select bit = 0) rom ram sfr internal address bus internal data bus internal code bus biu address 1 bus cycle = 2 biu internal address bus internal data bus internal code bus address 1 bus cycle = 2 1 bus cycle = 2 (internal rom bus cycle select bit = 1) biu internal address bus internal data bus internal code bus address data 1 bus cycle = 3 data data note: when reprogramming the internal flash memory in the cpu reprogramming mode, select the bus cycle = 3 . number of bus cycles figure 17 shows the bus cycle waveform at access to the internal area. bit 7 of the processor mode register 1 (address 5f 16 ) selects the number of bus cycles for the internal rom: 3 or 2 . (this bit 7 is the internal rom bus cycle select bit.) the internal ram, sfrs (in- ternal peripheral devices control registers) are always accessed with 1 bus cycle = 2 . figure 18 shows the bus cycle waveform at access to the external area. the bus cycle select bits 0, 1 (see the note in ___ figure 18.) select the number of the bus cycles for each cs i area from 8 types of numbers.
m37902fcchp, m37902fgchp, m37902fjchp mitsubishi microcomputers 26 shingle-chip 16-bit cmos microcomputer fig. 18 bus cycle types at access to external area 1 0 0 1 0 0 bus cycle select bit 1 = 0 bus cycle select bit 0 rd blw,bhw rd blw,bhw 1 external address bus external data bus cs i rd blw,bhw ale address 1 bus cycle = 2 1 external address bus external data bus cs i ale address 1 bus cycle = 3 1 external address bus external data bus cs i ale address 1 bus cycle = 4 1 external address bus external data bus cs i ale address 1 bus cycle = 4 data data data data rd blw,bhw 1 1 bus cycle select bit 1 = 1 rd blw,bhw 1 bus cycle = 5 1 external address bus external data bus cs i ale address 3 rd blw,bhw 1 bus cycle = 6 1 external address bus external data bus cs i ale address 4 2 2 rd blw,bhw 1 bus cycle = 6 1 external address bus external data bus cs i ale address 3 3 rd blw,bhw 1 bus cycle = 7 1 external address bus external data bus cs i ale address 4 3 data data data data bus cycle 1 + 1 ? bus cycle 1 + 2 ? bus cycle 1 + 3 ? bus cycle 2 + 2 bus cycle 2 + 3 bus cycle 2 + 4 bus cycle 3 + 3 bus cycle 3 + 4 ? ? notes 1: the bus cycle type is determined by the following bits: areas out of area cs i : external bus cycle select bit 0 (bits 2 and 3 at address 5e 16 ) external bus cycle select bit 1 (bit 0 at address 5f 16 ) area cs i : area cs i bus cycle select bit 0 (bits 0 and 1 at addresses 80 16 , 82 16 , 84 16 , 86 16 ) area cs i bus cycle select bit 1 (bit 3 at addresses 81 16 , 83 16 , 85 16 , 87 16 ) 2: ? indicates the bus cycle, where the burst rom access specification is enabled.
m37902fcchp, m37902fgchp, m37902fjchp 27 mitsubishi microcomputers shingle-chip 16-bit cmos microcomputer fig. 19 waveform example when recovery cycle is inserted at instruction prefetch at double consecutive access at quadruple consecutive access recovery cycle = 1 cycle of 1 recovery cycle = 2 cycles of 1 1 a 0 to a 23 ale rd address address + 2 1 a 0 to a 23 ale rd address address + 2 address + 4 1 a 0 to a 23 ale rd address address + 2 instruction prefetch recovery cycle next access cycle instruction prefetch recovery cycle next access cycle ? when address locates at 4-byte boundary, or when branched. ? ?? address + 6 instruction prefetch recovery cycle next access cycle 1 a 0 to a 23 ale rd address address + 2 address + 4 address + 6 instruction prefetch recovery cycle next access cycle ?? when address locates at 8-byte boundary. at data access 1 a 0 to a 23 ale rd, address access cycle recovery cycle next access cycle blw, bhw 1 a 0 to a 23 ale rd, address access cycle recovery cycle next access cycle blw, bhw notes 1: the recovery cycle insert is specified by the recovery cycle insert select bit and the recovery-cycle-insert-number select bit (bits 4 and 6 at address 5f 16 ). recovery cycle insertion is valid only at access to area cs i . 2: the above is applied when 1 bus cycle = 2 . recovery cycle a recovery cycle which is equivalent to 1 or 2 cycles of 1 can be in- ___ serted after each area cs i s access cycle. whether the recovery cycle is inserted or not is determined by the recovery cycle insert ___ select bit of each cs i control register l (bit 6 at addresses 80 16 , 82 16 , 84 16 , 86 16 ). also, the number of the recovery cycles is selected by the recovery-cycle-insert-number select bit of the processor mode register 1 (bit 6 at address 5f 16 ). figure 19 shows a waveform ex- ample when a recovery cycle is inserted.
m37902fcchp, m37902fgchp, m37902fjchp mitsubishi microcomputers 28 shingle-chip 16-bit cmos microcomputer burst rom access when rom supporting the burst rom access has been allocated to ___ area cs i , the burst rom access can be specified. the burst rom ___ access is specified by each burst rom access select bit of the cs i control register l (bit 5 at addresses 80 16 , 82 16 , 84 16 , 86 16 ). the burst rom access is valid only when the external data bus width = 16 bits with an instruction prefetched. in the other cases, the normal access is performed regardless of the contents of the burst rom ac- cess select bit. the burst rom access can be specified only in the case of ? in figure 18. figure 20 shows a waveform example at burst rom access. when an instruction is prefetched from the burst rom, 8 bytes are fetched starting from an 8-byte boundary (the low-order 3 bits of ad- dress, a 2 , a 1 , a 0 = 000 ) in waveform (a). when branched, regard- less of the 8-byte boundary of the branch destination address, access starting from the 4-byte boundary (the low-order 2 bits of ad- dress, a 1 , a 0 = 00 ) is performed in waveform (b). once the 8-byte boundary has been selected, instructions will be prefetched in wave- form (a) until a branch. fig. 20 waveform example at burst rom access note: the above is applied when 1 bus cycle = 2 . (b) external address bus rd external data bus data (instruction) external data bus data (instruction) data (instruction) data (instruction) address address (a) external address bus (a 0 to a 23 ) rd external data bus (d 0 to d 7 ) data (instruction) external data bus data (instruction) data (instruction) data (instruction) 1 address address address address data (instruction) data (instruction) data (instruction) data (instruction) (d 8 to d 15 ) (a 0 to a 23 ) (d 0 to d 7 ) (d 8 to d 15 ) 1 at quadruple consecutive access at double consecutive access note: the above is applied when 1 bus cycle = 2 . notes 1: the burst rom access is selected by the burst rom access select bit (bit 5 at addresses 80 16 , 82 16 , 84 16 , 86 16 ). 2: the burst rom access can be selected only in the case of ? in figure 18.
m37902fcchp, m37902fgchp, m37902fjchp 29 mitsubishi microcomputers shingle-chip 16-bit cmos microcomputer address output selection as shown in figure 21, the unnecessary state change of address output pins (a 0 to a 23 ) can be avoided, without outputting an address at access to the internal area. when the address output select bit of the particular function select register 1 (bit 4 at address 63 16 ) is set to 1 , an address is output only at access to the external area. also, at access to the internal area, the address at the preceding access to the external area is re- tained. the address output start timing in this case is the half cycle of 1 later than that at the normal access (when the address output select bit = 0 ). for the bit structure of the particular function select register 1, refer to the section on the standby function. also, at the normal access, an address is output at both of the ac- cess to the internal and external areas. fig. 21 waveform example depending on address output function selection access to external area 1 rd, blw,bhw a 0 to a 23 rd, blw,bhw a 0 to a 23 access to external area address output select bit = 0 address output select bit = 1 (address waveform changes only when external access is generated.) access to internal area address address address address unde- fined unde- fined
m37902fcchp, m37902fgchp, m37902fjchp mitsubishi microcomputers 30 shingle-chip 16-bit cmos microcomputer area multiplication ___ when area cs 2 s external data bus width = 8 bits with the multi- ___ plexed bus select bit of the cs 2 control register h (bit 5 at address 85 16 ) = 1 , the external bus type can be changed to the multiplexed ___ bus type only at access to area cs 2 . in this case, the low-order 8 bits of an address (la 0 to la 7) are output, and the low-order 8 bits of data (d 0 to d 7) are input/output with the time-sharing method, re- spectively. figure 22 shows a waveform example of area multiplication for each bus cycle. do not select the area multiplication function for a bus cycle not shown in figure 22. fig. 22 waveform example of area multiplication for each bus cycle d 0 to d 7 1 1 1 0 1 1 multiplexed bus select bit = 1 bus cycle select bit 0 rd, blw 1 bus cycle = 6 1 cs i ale 3 3 rd, blw 1 bus cycle = 7 1 cs i ale 4 3 d 0 to d 7 d 0 to d 7 d 0 to d 7 external address bus address external address bus address bus cycle 2 + 2 bus cycle 3 + 3 bus cycle 3 + 4 rd, blw 1 at write, la 0 /d 0 to la 7 /d 7 cs i ale d 0 to d 7 1 bus cycle = 4 d 0 to d 7 external address bus address 0 1 1 area cs 2 bus cycle select bit 0 at read, la 0 /d 0 to la 7 /d 7 at write, la 0 /d 0 to la 7 /d 7 at read, la 0 /d 0 to la 7 /d 7 at write, la 0 /d 0 to la 7 /d 7 at read, la 0 /d 0 to la 7 /d 7 la 0 to la 7 la 0 to la 7 la 0 to la 7 la 0 to la 7 la 0 to la 7 la 0 to la 7 notes 1: the number of bus cycles is determined by the following bits: area cs 2 bus cycle select bit 0 (bits 0 and 1 at address 84 16 ) area cs 2 bus cycle select bit 1 (bit 3 at address 85 16 ) area multiplication is specified by the multiplexed bus select bit (bit 5 at address 85 16 ). 2: do not select the area multiplication function for a bus cycle not shown in figure 22. 2 2
31 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers processor modes any of the three processor modes (single-chip mode, memory ex- pansion mode, microprocessor mode) can be selected with the fol- lowing: ?processor mode bits of the processor mode register 0 (bits 1 and 0 at address 5e 16 ; figure 24) ?voltage level applied to pin md0 table 3 lists the selection method of a processor mode. the memory map which the cpu can access depends on the se- lected processor mode. figure 23 shows the memory maps in three processor modes. also, the functions of ports p0 to p4, p10, p11 depend on the se- lected processor mode. for details, see tables 5 and 6. figures 24 to 26 show the bit configurations of the processor mode registers 0, 1, and port function control register. in the single-chip mode, ports p0 to p4, p10, p11 function as i/o ports. (while the internal peripheral devices are used, these ports function as these devices?i/o pins.) in this mode, only the internal area (sfrs, internal ram, internal rom) is accessible. in the memory expansion and microprocessor modes, external de- vices assigned in the external memory area can be connected via buses. therefore, ports p0 to p4, p10, p11 function as i/o pins for the address bus, data bus, bus control signals. (some port functions are selectable.) table 4 lists each bus control signals function. in the memory expansion mode, all of the internal area (sfrs, inter- nal ram, internal rom) and external area are accessible. in the mi- croprocessor mode, the internal area except for the internal rom (in other words, sfrs and internal ram) and the external area are ac- cessible. note that, when the external devices are located to an area where the internal area and external area overlap, only the internal area can be read/written; the external area cannot be read/written. single-chip mode sfr area unused area unused area internal ram area internal rom area memory expansion mode sfr area internal ram area internal rom area reserved area (note) microprocessor mode sfr area internal ram area reserved area (note) 0 16 ff 16 feffff 16 ff0000 16 ffffff 16 external area : access to this area enables the access to the devices which are connected with the external. note: do not access this area (bank ff 16 ). sfr area : internal peripheral devices control registers are allocated here. fig. 23 memory maps in three processor modes
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 32 signal rd blw bhw ale 1 rdy hold hdla cs 0 ?s 3 byte v ss v cc 00 01 10 10 md0 processor mode bits after reset is removed, the single-chip mode is selected. by chang- ing the processor mode bits?contents by software, the memory ex- pansion mode or microprocessor mode can be selected. description (note 1) processor mode after reset is removed, the microprocessor mode is selected. (note 2) single-chip mode memory expansion mode microprocessor mode microprocessor mode table 3. selection method of processor mode table 4. each bus control signal? function i/o output output output output input input output output input function read signal. outputs ??at read from the external area. write signal. outputs ??at write to the external area. address latch enable signal. outputs ??level pulse in the period just before signals rd, blw, bhw become ?? this is used to latch an address in an external circuit. internal standard clocks output. outputs system clock (f sys ). ready signal. the ??level period of the last 1 in the ac- cess cycle for the external area (in other words, ??level period of rd, blw, bhw) will be extended while ??level voltage is applied to this pin. hold request signal. appliance of ??level voltage will gen- erate a hold request; appliance of ??level voltage will re- quest to terminate the hold state. hold acknowledge signal. outputs ??in the hold state. chip select signal. outputs ??in access to the specified chip select area. input signal to select the external data bus width. when this pins level = vss, 16-bit width will be selected; and when vcc, 8-bit width will be selected. remarks for operation differences between blw and bhw de- pending on the external data bus width, see table 5. in order to latch an address with signal ale, do as follows: ?while ale = ?? be sure to open a latch, so the address will pass it. ?while ale = ?? be sure to hold the address. acceptance and termination of a hold request is performed at completion of the bus cycle while the biu operates. in the hold state, a 0 ? 23 , d 0 ? 15 , rd, blw, bhw, ale, cs 0 ?s 3 enter the floating state. at termination of the hold state, simultaneously with the timing when hlda becomes ??level, the above floating state is terminated. then, bus access will be restarted 1 cycle of 1 after. in the hold state, also, the cpu operates with access to the internal area. if the cpu accesses the external area, in the hold state, the cpu stops its operation. for details, refer to the section on the chip select wait con- troller. when byte = vss level, by the register setting, each chip select area (cs 1 to cs 3 ) can have the 8-bit data bus, inde- pendently. for details, refer to the section on the chip select wait con- troller. notes 1: processor mode bits = bits 0 and 1 of the processor mode register 0 (address 5e 16 ) 2: while the vcc level voltage is applied to pin md0, the processor mode bits are fixed to ?0?
33 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers microprocessor mode v cc level voltage is applied 10 sfr area internal ram area external memory area external memory area low-order address (a 0 to a 7 ) is output. middle-order address (a 8 to a 15 ) is output. i/o port pins p11 0 to p11 7 (note 3) high-order address (a 16 to a 23 ) is out- put. i/o port pins p0 0 to p0 7 (note 3) low-order data (d 0 to d 7 , data at even address) is input/output. low-order data (d 0 to d 7 , data at even/odd address) is input/output. low-order address (la 0 to la 7 ) is out- put. low-order data (d 0 to d 7 , data at even/odd address) is input/output (note 4) . high-order data (d 8 to d 15 , data at odd address) is input/output. i/o port pins p2 0 to p2 7 (note 5) ready signal rdy is input. i/o port pin p3 0 (note 6) read signal rd is output write signal blw (write to even ad- dress) is output. write signal blw (write to even/odd address) is output. write signal bhw (write to odd ad- dress) is output. i/o port pin p3 3 (note 5) memory expansion mode v ss level voltage is applied 01 sfr area internal ram area internal rom area external memory area low-order address (a 0 to a 7 ) is output. middle-order address (a 8 to a 15 ) is output. i/o port pins p11 0 to p11 7 (note 3) high-order address (a 16 to a 23 ) is out- put. i/o port pins p0 0 to p0 7 (note 3) low-order data (d 0 to d 7 , data at even address) is input/output. low-order data (d 0 to d 7 , data at even/odd address) is input/output. low-order address (la 0 to la 7 ) is out- put. low-order data (d 0 to d 7 , data at even/odd address) is input/output (note 4) . high-order data (d 8 to d 15 , data at odd address) is input/output. i/o port pins p2 0 to p2 7 (note 5) i/o port pin p3 0 ready signal rdy is input (note 6). read signal rd is output. write signal blw (write to even ad- dress) is output. write signal blw (write to even/odd address) is output. write signal bhw (write to odd ad- dress) is output. i/o port pin p3 3 (note 5) table 5. relationship between processor modes, memory area, and port function (1) mode (note 1) single-chip mode v ss level voltage is applied 00 sfr area internal ram area internal rom area (do not access.) i/o port pins p10 0 to p10 7 i/o port pins p11 0 to p11 7 i/o port pins p0 0 to p0 7 i/o port pins p1 0 to p1 7 i/o port pins p2 0 to p2 7 i/o port pin p3 0 i/o port pin p3 1 i/o port pin p3 2 i/o port pin p3 3 memory area port pins p10 0 to p10 7 port pins p11 0 to p11 7 port pins p0 0 to p0 7 port pins p1 0 to p1 7 external data bus width = 16 bits external data bus width = 8 bits external data bus width = 8 bits port pins p2 0 to p2 7 port pin p3 0 port pin p3 1 external data bus width = 16 bits external data bus width = 8 bits external data bus width = 16 bits port pin p3 2 port pin p3 3 external data bus width = 8 bits pin md0 processor mode bits (note 2) sfr area internal ram area internal rom area other area external data bus width = 16 bits
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 34 notes 1: for details of the processor mode setting, see table 3. 2: processor mode bits = bits 0 and 1 of the processor mode register 0 (address 5e 16). 3: the middle-order/high-order address output pins in the memory expansion or microprocessor mode can be switched to i/o port pins by the address/port switch select bits of the port function control register (bits 2 to 0 at address 92 16 ). 4: when the external data bus width for the chip select area, cs 2 , has been set to 8 bits, only in the access to area cs 2 , by the multiplexed bus select bit of the cs 2 control register h (bit 5 at address 85 16 ), a multiplexed bus which performs the following operations with the time-sharing method is realized: output of address la 0 to la 7 input/output of data d 0 to d 7 5: when one of areas cs 1 /cs 2 /cs 3 is accessed under the following conditions, pins d 8 to d 15 enter the floating state, and pin bhw outputs h level. (they do not become i/o port pins.) pin byte is at vss level. one of bit 2s at addresses 82 16 , 84 16 , 86 16 (the external data bus width select bit of the cs 1 /cs 2 /cs 3 control register l) is set to 1 (external data bus width = 8 bits). 6: in the memory expansion mode, by the corresponding select bits of the processor mode register 0 and 1 (addresses 5e 16 , 5f 16 ), port pins p3 0 , p4 0 to p4 3 can operate as pins for rdy input, ale output, 1 output, hlda output, hold input, respectively. in the microprocessor mode, by the above select bits, the above pins (rdy, ale, 1 , hlda, hold) can operate as port pins p3 0 , p4 0 to p4 3 , respec- tively. in the single-chip mode, port pin p4 1 can operate as the 1 output pin by the above select bits. 7: in the memory expansion mode, port pin p4 4 can operate as the cs 0 output pin by the cs 0 output select bit of the cs 0 control register l (bit 7 at address 80 16 ). 8: in the memory expansion and microprocessor modes, port pins p4 5 to p4 7 can operate as the cs 1 /cs 2 /cs 3 output pins by the cs i output select bits (i = 1 to 3) (bit 7s at addresses 82 16 , 84 16 , 86 16 ). table 6. relationship between processor modes, memory area, and port function (2) single-chip mode i/o port pin p4 0 i/o port pin p4 1 clock 1 is output (note 6). i/o port pin p4 2 i/o port pin p4 3 i/o port pin p4 4 i/o port pins p4 5 to p4 7 port pin p4 0 port pin p4 1 port pin p4 2 port pin p4 3 port pin p4 4 port pins p4 5 to p4 7 memory expansion mode i/o port pin p4 0 address latch enable signal ale is output (note 6) . i/o port pin p4 1 clock 1 is output (note 6) . i/o port pin p4 2 hold acknowledge signal hlda is output (note 6) . i/o port pin p4 3 hold request signal hold is input (note 6) . i/o port pin p4 4 chip select signal cs 0 is output (note 7) . i/o port pins p4 5 to p4 7 chip select signals cs 1 to cs 3 are output (note 8) . microprocessor mode address latch enable signal ale is output. i/o port pin p4 0 (note 6) clock 1 is output. i/o port pin p4 1 (note 6) hold acknowledge signal hlda is output. i/o port pin p4 2 (note 6) hold request signal signal hold is input. i/o port pin p4 3 (note 6) chip select signal cs 0 is output. i/o port pin p4 5 to p4 7 chip select signals cs 1 to cs 3 are output (note 8) .
35 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers fig. 24 bit configuration of processor mode register 0 notes 1: while v ss level voltage is applied to pin md0, this bit s state is cleared to 0 at reset. while v cc level voltage is applied to pin md0, on the other hand, this bit s state is set to 1 at reset. (fixed to 1 .) 2: these bits are valid to the external area except for chip select area (area cs i ). the bus cycle of area cs i is selected by the corresponding area cs i bus cycle select bits 0, 1. 3: while v ss level voltage is applied to pin md0, this bit s state is cleared to 0 at reset. while v cc level voltage is applied to pin md0, on the other hand, this bit s state is set to 1 at reset. 76543210 processor mode register 0 processor mode bits (note 1) 0 0 : single-chip mode 0 1 : memory expansion mode 1 0 : microprocessor mode 1 1 : do not select. interrupt priority detection time select bits 0 0 : 7 cycles of f sys 0 1 : 4 cycles of f sys 1 0 : 2 cycles of f sys 1 1 : do not select. software reset bit by a write of 1 to this bit, the microcomputer will be reset, and then, restarted. external bus cycle select bit 0 (note 2) see figure 18. clock 1 output select bit (note 3) 0 : 1 output is disabled. (p4 1 functions as an programmable i/o port pin.) 1 : 1 output is enabled. (p4 1 functions as the clock 1 output pin.) address 5e 16
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 36 fig. 25 bit configuration of processor mode register 1 notes 1: this bit is valid to the external area except for chip select areas (area cs i ), and the bus cycle of area cs i is independent of this bit s contents. the bus cycle of area cs i is selected by the corresponding area cs i bus cycle select bits 0, 1 (bits 0, 1 at addresses 80 16 , 82 16 , 84 16 , 86 16 ; bit 3 at addresses 81 16 , 83 16 , 85 16 , 87 16 ). 2: after reset, this bit s contents can be switched only once. during the software execution, be sure not to switch this bit s contents. 3: in the single-chip mode, these bits functions are disabled regardless of these bits contents. 4: while v ss level voltage is applied to pin md0, each of these bits is 0 at reset. while v cc level voltage is applied to pin md0, on the other hand, each of these bits is 1 at reset. 5: in the memory expansion or microprocessor mode, if this bit s contents is switched from 1 to 0 , this bit will be cleared to 0 . after this clearance, this bit cannot return to 1 . if it is necessary to set this bit to 1 , be sure to reset the microcomputer. 6: the program which switches this bit s contents must be assigned to the internal area. 7: in the microprocessor mode, this bit is invalid. when the internal flash memory is reprogrammed in the cpu reprogramming mode, be sure to clear this bit to 0 . 76543210 processor mode register 1 external bus cycle select bit 1 (note 1) see figure 18. rdy input select bit (notes 3 to 5) 0 : rdy input is disabled. (p3 0 functions as a programmable i/o port pin.) 1 : rdy input is enabled. (p3 0 functions as pin rdy.) ale output select bit (notes 3 and 4) 0 : ale output is disabled. (p4 0 functions as a programmable i/o port pin.) 1 : ale output is enabled. (p4 0 functions as pin ale.) direct page register switch bit (note 2) 0 : only dpr0 is used. 1 : dpr0 to dpr3 are used. recovery cycle insert select bit (notes 3 and 4) 0 : no recovery cycle is inserted at access to the external area. 1 : recovery cycle is inserted at access to the external area. address 5f 16 hold input, hlda output select bit (notes 3 to 5) 0 : hold input and hlda output are disabled. (p4 3 and p4 2 function as programmable i/o port pins.) 1 : hold input and hlda output are enabled. (p4 3 and p4 2 function as pins hold and hlda, respectively.) recovery-cycle-insert number select bit (note 6) 0 : 1 cycle 1 : 2 cycles internal rom bus cycle select bit (note 7) 0 : 3 1 : 2
37 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers fig. 26 bit configuration of port function control register notes 1: for the m37902fxm (power source voltage = 3.3 v 0.3 v), v ih = 0.5v cc . 2: when md1 = v cc and md0 = v cc (flash memory parallel i/o mode), pins p4 4 to p4 7 and nmi are not pulled up, regardless of these bits contents. 3: when md1 = v ss and md0 = v cc (microprocessor mode), pin cs 0 (p4 4 ) is not pulled up, regardless of the bit s contents. 76543210 port function control register port p0 input level select bit 0 : v ih = 0.7v cc , v il = 0.2v cc 1 : v ih = 0.43v cc (note 1) , v il = 0.16v cc address/port switch select bits 000 : a 0 to a 23 (16 mbytes) 001 : a 0 to a 21 , p0 6 , p0 7 (4 mbytes) 010 : a 0 to a 19 , p0 4 to p0 7 (1 mbytes) 011 : a 0 to a 17 , p0 2 to p0 7 (256 kbytes) 100 : a 0 to a 15 , p0 0 to p0 7 (64 kbytes) 101 : do not select. 110 : a 0 to a 11 , p0 0 to p0 7 , p11 4 to p11 7 (4 kbytes) 111 : a 0 to a 7 , p0 0 to p0 7 , p11 0 to p11 7 (256 bytes) pins p4 4 p4 7 pullup select bit (notes 2 and 3) 0 : pins p4 4 p4 7 are pulled up. 1 : pins p4 4 p4 7 are not pulled up. address 92 16 pin nmi pullup select bit (note 2) 0 : pin nmi is pulled up. 1 : pin nmi is not pulled up. fix these bits to 0 . 0 0 at reset 00 16
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 38 chip select wait controller by the control of the chip select wait controller (cswc), the chip se- lect function for the maximum of 4 blocks can be set at the bus ac- cess to the external area. also, by the setting of the cswc, port pins p4 4 to p4 7 can operate as chip select output pins (cs 0 to cs 3 ). figure 27 shows a chip select output waveform example. this chip select function determines the following items of the chip select area: start address, address s block size, wait number, exter- nal data bus width, rdy control validity, burst rom specification, recovery cycle insertion validity, and area multiplication validity. for the external area except for areas cs 0 to cs 3 , the processor mode registers 0, 1 determine the above items. after reset is re- moved, when the microcomputer starts it s operation in the micropro- cessor mode, area cs 0 is automatically selected. table 7 lists the function of areas cs 0 to cs 3 . figure 28 shows the bit configuration of the cs 0 /cs 1 /cs 2 /cs 3 con- trol register ls. these registers determine the following items of a device to be connected: wait number, external data bus width ( note: the external data bus width of area cs 0 is determined by pin byte s level.), rdy control validity, burst rom access specification, recov- ery cycle insertion validity, and output validity of cs 0 to cs 3 . figure 29 shows the bit configuration of the cs 0 /cs 1 /cs 2 /cs 3 con- trol register hs. these registers determine block size, etc. of an ex- ternal area to be connected. for areas cs 0 to cs 2 , by selecting mode 1 with the area csk setting mode select bit, an chip select area can be set to the external area in bank 0. figures 30 shows the bit configuration of the area cs 0 /cs 1 /cs 2 /cs 3 start address registers. for details of these addresses setting, see figures 31 to 33. when area cs i is accessed 1 a 0 to a 23 ale rd, when the same area cs i is accessed sequentially 1 a 0 to a 23 ale rd, address + 2 one access cycle address one access cycle address cs i blw, bhw blw, bhw one access cycle cs i fig. 27 chip select output waveform example
39 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers bus cycle: 1 + 1 1 + 2 1 + 3 2 + 2 2 + 3 2 + 4 3 + 3 3 + 4 (selected by bits 2, 3 at address 5e 16 and bit 0 at address 5f 16 .) determined by pin byte s level valid (selected by bit 2 at address 5f 16 .) not available. available. not available. available. cs 3 banks 2 16 to fe 16 128 kbytes, 256 kbytes, 512 kbytes, 1 mbytes, 2 mbytes, 4 mbytes, or 8 mbytes bus cycle: 1 + 1 1 + 2 1 + 3 2 + 2 2 + 3 2 + 4 3 + 3 3 + 4 (selected by bits 0, 1 at address 86 16 and bit 3 at address 87 16 .) when byte = v ss level, 8-bit width or 16-bit width can be selected arbitrary (note 1) . (selected by bit 2 at address 86 16 .) valid (selected by bit 2 at address 5f 16 and bit 3 at address 86 16 .) available. available. not available. available. bus cycle: 1 + 1 1 + 2 1 + 3 2 + 2 2 + 3 2 + 4 3 + 3 3 + 4 (selected by bits 0, 1 at addresses 82 16 , 84 16 and bit 3 at addresses 83 16 , 85 16 .) when byte = v ss level, 8-bit width or 16-bit width can be selected arbitrary (note 1) . (selected by bit 2 at addresses 82 16 , 84 16 .) valid (selected by bit 2 at address 5f 16 and bit 3 at addresses 82 16 , 84 16 .) available. available. cs 1 : not available. cs 2 : available. (note 4) available. space where start address can be set block size bus cycle external data bus width rdy control burst rom access (notes 2, 3) recovery cycle insertion area multiplexed bus access (note 3) address output selection (note 5) bus cycle: 1 + 1 1 + 2 1 + 3 2 + 2 2 + 3 2 + 4 3 + 3 3 + 4 (selected by bits 0, 1 at address 80 16 and bit 3 at address 81 16 .) determined by pin byte s level. valid (selected by bit 2 at address 5f 16 and bit 3 at address 80 16 .) available. available. not available. available. cs 0 mode 0 banks 2 16 to fe 16 128 kbytes, 256 kbytes, 512 kbytes, 1 mbytes, 2 mbytes, 4 mbytes, or 8 mbytes mode 1 bank 0 16 128 kbytes, 256 kbytes, 512 kbytes, 1 mbytes, 2 mbytes, 4 mbytes, or 8 mbytes cs 1 , cs 2 mode 0 banks 2 16 to fe 16 128 kbytes, 256 kbytes, 512 kbytes, 1 mbytes, 2 mbytes, 4 mbytes, or 8 mbytes mode 1 bank 0 16 4 kbytes or 8 kbytes external area except for cs 0 to cs 3 table 7. function of areas cs 0 to cs 3 notes 1: when byte = vcc level, the external data bus width is fixed to 8 bits. 2: burst rom access is valid only when the external data bus width is 16 bits at instruction prefetch. 3: burst rom access and area multiplexed bus access cannot be used at the same time. 4: valid only when area cs 2 is accessed with the 8-bit external data bus width. 5: selected by the address output select bit (bit 4 at address 63 16 ). the address output selection for each area is not available.
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 40 fig. 28 bit configuration of cs 0 /cs 1 /cs 2 /cs 3 control register ls 76543210 cs 0 control register l external data bus width select bit (note 1) 0 : 16-bit width 1 : 8-bit width rdy control bit (note 2) 0 : rdy control is valid. 1 : rdy control is invalid. area cs 0 bus cycle select bit 0 see figure 18. address 80 16 at reset 42 16 burst rom access select bit (note 3) 0 : normal access 1 : burst rom access recovery cycle insert select bit 0 : no recovery cycle is inserted at access to area cs 0 . 1 : recovery cycle is inserted at access to area cs 0 . cs 0 output select bit (notes 4, 5) 0 : cs 0 output is disabled. (p4 4 functions as a programmble i/o port pin.) 1 : cs 0 output is enabled. (p4 4 functions as pin cs 0 .) notes 1: while v ss level voltage is applied to pin byte, this bit s state is cleared to 0 at reset. while v cc level voltage is applied to pin byte, on the other hand, this bit s state is set to 1 at reset. 2: this bit is valid when the rdy input select bit (bit 2 at address 5f 16 ) = 1 . 3: while v cc level voltage is applied to pin byte, the normal access is selected regardless of this bit s contents. 4: in the single-chip mode, this bit s contents are invalid. (cs 0 output is disabled.) 5: while v ss level voltage is applied to pin md0, this bit s state is cleared to 0 at reset. while v cc level voltage is applied to pin md0, on the other hand, this bit s state is set to 1 at reset. (fixed to 1 .) 76543210 cs 1 control register l cs 2 control register l cs 3 control register l external data bus width select bit 0 : 16-bit width 1 : 8-bit width (note 1) rdy control bit (note 2) 0 : rdy control is valid. 1 : rdy control is invalid. area cs j bus cycle select bit 0 (j = 1 to 3) see figure 18. 0 at reading. address 82 16 84 16 86 16 at reset 42 16 42 16 42 16 burst rom access select bit (note 3) 0 : normal access 1 : burst rom access recovery cycle insert select bit 0 : no recovery cycle is inserted at access to area cs j . 1 : recovery cycle is inserted at access to area cs j . cs j output select bit (j = 1 to 3) (note 4) 0 : cs j output is disabled. (p4 5 to p4 7 function as programmable i/o port pins.) 1 : cs j output is enabled. (p4 5 to p4 7 function as pin cs j .) notes 1: while v cc level voltage is applied to pin byte, this bit is fixed to 1 (8-bit width). 2: this bit is valid when the rdy input select bit (bit 2 at address 5f 16 ) = 1 . 3: when only the external data bus width select bit (bit 2) = 1 or while v cc level voltage is applied to pin byte, the normal access is selected regardless of this bit s contents. 4: in the single-chip mode, this bit s contents are invalid. (cs 0 output is disabled.) 0 at read.
41 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers fig. 29 bit configuration of cs 0 /cs 1 /cs 2 /cs 3 control register hs area cs 3 bus cycle select bit 1 see figure 18. area cs 1 bus cycle select bit 1 see figure 18. area cs 0 bus cycle select bit 1 see figure 18. 76543210 cs 0 control register h area cs 0 block size select bit when mode 0 is selected 0 0 0 : 0 byte (area cs 0 is invalid.) 0 0 1 : 128 kbytes 0 1 0 : 256 kbytes 0 1 1 : 512 kbytes 1 0 0 : 1 mbytes 1 0 1 : 2 mbytes 1 1 0 : 4 mbytes 1 1 1 : 8 mbytes address 81 16 at reset 81 16 at reset 00 16 76543210 cs 1 control register h area cs 1 block size select bit address 83 16 when mode 0 is selected 0 0 0 : 0 byte (area cs 1 is invalid.) 0 0 1 : 128 kbytes 0 1 0 : 256 kbytes 0 1 1 : 512 kbytes 1 0 0 : 1 mbytes 1 0 1 : 2 mbytes 1 1 0 : 4 mbytes 1 1 1 : 8 mbytes when mode 1 is selected 0 0 0 : 0 byte (area cs 1 is invalid.) 0 0 1 : do not select. 0 1 0 : do not select. 0 1 1 : do not select. 1 0 0 : 4 kbytes 1 0 1 : 8 kbytes 1 1 0 : do not select. 1 1 1 : do not select. when mode 1 is selected 0 0 0 : 0 byte (area cs 0 is invalid.) 0 0 1 : 128 kbytes 0 1 0 : 256 kbytes 0 1 1 : 512 kbytes 1 0 0 : 1 mbytes 1 0 1 : 2 mbytes 1 1 0 : 4 mbytes 1 1 1 : 8 mbytes must be fixed to 0 . 76543210 cs 3 control register h area cs 3 block size select bit 0 0 0 : 0 byte (area cs 3 is invalid.) 0 0 1 : 128 kbytes 0 1 0 : 256 kbytes 0 1 1 : 512 kbytes 1 0 0 : 1 mbytes 1 0 1 : 2 mbytes 1 1 0 : 4 mbytes 1 1 1 : 8 mbytes address 87 16 area cs 1 setting mode select bit 0 : mode 0 (a block can be set to 16-mbyte space in a unit of 128 kbytes.) 1 : mode 1 (a block can be set to bank 0 in a unit of 4 kbytes.) area cs 0 setting mode select bit 0 : mode 0 (a block can be set to 16-mbyte space.) 1 : mode 1 (area cs 0 start address can be set to bank 0.) 0 at read. 0 at read. 0 at read. 0 at reset 00 16 at reset 00 16 76543210 cs 2 control register h area cs 2 block size select bit address 85 16 when mode 0 is selected 0 0 0 : 0 byte (area cs 2 is invalid.) 0 0 1 : 128 kbytes 0 1 0 : 256 kbytes 0 1 1 : 512 kbytes 1 0 0 : 1 mbytes 1 0 1 : 2 mbytes 1 1 0 : 4 mbytes 1 1 1 : 8 mbytes when mode 1 is selected 0 0 0 : 0 byte (area cs 2 is invalid.) 0 0 1 : do not select. 0 1 0 : do not select. 0 1 1 : do not select. 1 0 0 : 4 kbytes 1 0 1 : 8 kbytes 1 1 0 : do not select. 1 1 1 : do not select. multiplexed bus select bit 0 : separated bus (d 0 to d 7 are input/output.) 1 : multiplexed bus (when the cs 2 external data bus width = 8 bits with area cs 2 accessed, la 0 /d 0 to la 7 /d 7 are input/output.) area cs 2 setting mode select bit 0 : mode 0 (a block can be set to 16-mbyte space in a unit of 128 kbytes.) 1 : mode 1 (a block can be set to bank 0 in a unit of 4 kbytes.) area cs 2 bus cycle select bit 1 see figure 18. 0 at read.
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 42 76543210 area cs 0 start address register when mode 0 is selected, these bits determine a 16 to a 23 of the area cs 0 start address. when mode 1 is selected, these bits determine a 8 to a 15 of the area cs 0 start address. any of the following values can be set to these bits: 10 16 , 20 16 , 40 16 , and 80 16 . (bits 0 to 3 are always 0 at read.) address 8a 16 at reset 10 16 at reset 00 16 00 16 at reset 00 16 76543210 area cs 1 start address register area cs 2 start address register when mode 0 is selected, these bits determine a 16 to a 23 of the area cs 1 /cs 2 start address. when mode 1 is selected, these bits determine a 8 to a 15 of the area cs 1 /cs 2 start address. (bit 0 is always 0 at read.) address 8c 16 8e 16 76543210 area cs 3 start address register these bits determine a 16 to a 23 of the area cs 3 start address. (bit 0 is always 0 at read.) address 90 16 note: do not set a value other than 10 16 , 20 16 , 40 16 , and 80 16 . see figure 31. note: the start address setting depends on the block size, which has been selected by the area cs 1 /cs 2 block size select bits (bits 0 to 2 at address 83 16 , bits 0 to 2 at address 85 16 ). see figures 32 and 33. note: the start address setting depends on the block size, which has been selected by the area cs 3 block size select bits (bits 0 to 2 at address 87 16 ). see figure 33. 0 at read. 0 at read. 0 at read. fig. 30 bit configuration of area cs 0 /cs 1 /cs 2 /cs 3 start address registers
43 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers fig. 31 area cs 0 (mode 1) 128k bytes 512k bytes 2m bytes 1m bytes 4m bytes 8m bytes 128k bytes 512k bytes 2m bytes 256k bytes 1m bytes 4m bytes 8m bytes 0 16 1000 16 1ffff 16 7ffff 16 fffff 16 128k bytes 512k bytes 2m bytes start address : 1000 16 value to be set to area cs 0 start address register = 10 16 block size 2000 16 start address : 2000 16 value to be set to area cs 0 start address register = 20 16 4000 16 start address : 4000 16 value to be set to area cs 0 start address register = 40 16 8000 16 128k bytes start address : 8000 16 value to be set to area cs 0 start address register = 80 16 area cs 0 cannot be assigned here. note: when an area where area cs 0 and the internal area overlap is accessed, the internal area will be accessed. in this case, pin cs 0 outputs h level. 3ffff 16 256k bytes 1fffff 16 1m bytes 4m bytes 8m bytes 512k bytes 2m bytes 256k bytes 1m bytes 4m bytes 8m bytes 3fffff 16 7fffff 16 block size block size block size 256k bytes
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 44 fig. 32 area cs 1 /cs 2 (mode 1) 0 16 1000 16 2000 16 ( ffff 16 ) block size : 4 kbytes addresses which can be start address (address ffff 16 is not included; note 1 ) 3000 16 4000 16 5000 16 6000 16 7000 16 8000 16 0 16 2000 16 (ffff 16 ) block size : 8 kbytes addresses which can be start address (address ffff 16 is not included; note 1 ) 4000 16 6000 16 4 kbytes 8 kbytes f000 16 e0 0 0 16 8000 16 notes 1: only a 8 to a 15 of one of these addresses can be set to the area cs 1 /cs 2 start address register. do not set another address not shown here. 2: when an area where area cs 1 /cs 2 and the internal area overlap is accessed, the internal area will be accessed. in this case, pin cs 1 /cs 2 outputs h level.
45 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers fig. 33 area cs 0 /cs 1 /cs 2 (mode 0) and area cs 3 notes 1: only a 16 to a 23 of one of these addresses can be set to the area cs 0 /cs 1 /cs 2 /cs 3 start address register. do not set another address not shown here. 2: when an area where area cs 0 /cs 1 /cs 2 /cs 3 and the internal area overlap is accessed, the internal area will be accessed. in this case, pin cs 0 /cs 1 /cs 2 /cs 3 outputs h level. block size : 128 kbytes addresses which can be start address (addresses 0 16 and ff0000 16 to ffffff 16 are not included; note 1 ) : area cs 0 /cs 1 /cs 2 /cs 3 cannot be assigned here. (0 16 ) 20000 16 40000 16 60000 16 80000 16 a0000 16 c0000 16 e0000 16 100000 16 f60000 16 f80000 16 fa0000 16 fc0000 16 fe0000 16 ( ff0000 16 ) ( ffffff 16 ) 120000 16 block size : 256 kbytes addresses which can be start address (addresses 0 16 and ff0000 16 to ffffff 16 are not included; note 1 ) (0 16 ) 40000 16 80000 16 c0000 16 100000 16 f80000 16 fc0000 16 ( ff0000 16 ) ( ffffff 16 ) block size : 512 kbytes addresses which can be start address (addresses 0 16 and ff0000 16 to ffffff 16 are not included; note 1 ) (0 16 ) 80000 16 100000 16 f80000 16 ( ff0000 16 ) ( ffffff 16 ) block size : 1 mbytes addresses which can be start address (addresses 0 16 and ff0000 16 to ffffff 16 are not included; note 1 ) (0 16 ) 100000 16 200000 16 300000 16 400000 16 500000 16 600000 16 700000 16 800000 16 b00000 16 c00000 16 d00000 16 e00000 16 f00000 16 ( ff0000 16 ) ( ffffff 16 ) 900000 16 a00000 16 block size : 2 mbytes addresses which can be start address (addresses 0 16 and ff0000 16 to ffffff 16 are not included; note 1 ) (0 16 ) 200000 16 400000 16 600000 16 800000 16 c00000 16 e00000 16 ( ff0000 16 ) ( ffffff 16 ) a00000 16 block size : 4 mbytes addresses which can be start address (addresses 0 16 and ff0000 16 to ffffff 16 are not included; note 1 ) (0 16 ) 400000 16 800000 16 c00000 16 ( ff0000 16 ) ( ffffff 16 ) block size : 8 mbytes addresses which can be start address (addresses 0 16 and ff0000 16 to ffffff 16 are not included; note 1 ) (0 16 ) 800000 16 ( ff0000 16 ) ( ffffff 16 ) : reserved area. do not access this area.
m37902fcchp, m37902fgchp, m37902fjchp 46 mitsubishi microcomputers single-chip 16-bit cmos microcomputer interrupts table 8 shows the interrupt sources and the corresponding interrupt vector addresses. reset is also handled as a type of interrupt in this section, too. dbc and brk instruction are interrupts used only for debugging. therefore, do not use these interrupts. interrupts other than reset, watchdog timer, zero divide, nmi, and address matching detection all have interrupt control registers. table 9 shows the addresses of the interrupt control registers and figure 35 shows the bit configuration of the interrupt control register. the interrupt request bit is automatically cleared by the hardware during reset or when processing an interrupt. also, interrupt request bits other than watchdog timer and nmi can be cleared by software. an nmi interrupt request is a non-maskable interrupt by an external input and is accepted at the falling edge of an input to pin nmi. also, pin nmi has the pullup function. for more details, refer to the section on input/output pins. an int i (i = 0 to 4) interrupt request is generated by an external in- put. int 0 to int 2 are external interrupts; whether to cause an interrupt at the input level (level sense) or at the edge (edge sense) can be se- lected with the level/edge select bit. furthermore, the polarity of the interrupt input can be selected with the polarity select bit. for int 3 and int 4, the interrupt signals polarity can be change by the polarity select bit. (this is valid only in the edge sense.) by pins int 2 to int 4 select bits (bits 4 to 6 at address 94 16 ; see fig- ure 40.), pin position of int 2 to int 4 can be changed. when using the following pins as external interrupt input pins, clear the direction registers of the corresponding multiplexed ports to ?? pins p6 2 /int 0 , p6 3 /int 1 , p6 4 (p7 7 )/int 2 , p8 0 (p7 4 )/int 3 , and p8 4 (p7 5 )/int 4 . furthermore, the int 3 interrupt can function as the key input inter- rupt. for details, refer to the section on the key input interrupt. when the external interrupt input read register (address 95 16 ) is read out, the status of pins int 0 to int 4 and nmi can directly be read. timer and uart interrupts are described in the respective section. the priority of interrupts when multiple interrupt requests are caused simultaneously is partially fixed by hardware, but, it can also be ad- justed by software as shown in figure 36. the hardware priority is fixed as the following: reset > nmi > watchdog timer > other interrupts interrupts address matching detection interrupt int 4 external interrupt int 3 external interrupt a-d conversion uart1 transmit uart1 receive uart0 transmit uart0 receive timer b2 timer b1 timer b0 timer a4 timer a3 timer a2 timer a1 timer a0 int 2 external interrupt int 1 external interrupt int 0 external interrupt nmi external interrupt watchdog timer dbc (do not select.) break instruction (do not select.) zero divide reset table 8. interrupt sources and interrupt vector addresses vector addresses 00ffca 16 00ffcb 16 00ffd0 16 00ffd1 16 00ffd2 16 00ffd3 16 00ffd4 16 00ffd5 16 00ffd6 16 00ffd7 16 00ffd8 16 00ffd9 16 00ffda 16 00ffdb 16 00ffdc 16 00ffdd 16 00ffde 16 00ffdf 16 00ffe0 16 00ffe1 16 00ffe2 16 00ffe3 16 00ffe4 16 00ffe5 16 00ffe6 16 00ffe7 16 00ffe8 16 00ffe9 16 00ffea 16 00ffeb 16 00ffec 16 00ffed 16 00ffee 16 00ffef 16 00fff0 16 00fff1 16 00fff2 16 00fff3 16 00fff4 16 00fff5 16 00fff6 16 00fff7 16 00fff8 16 00fff9 16 00fffa 16 00fffb 16 00fffc 16 00fffd 16 00fffe 16 00ffff 16 fig. 34 bit configuration of external interrupt input read register 76543210 note: when the key input interrupt select bit (bit 0 at address 94 16 ) = 1 , the status of pin int 3 cannot be read out. int 0 read bit int 1 read bit int 2 read bit int 3 read bit (note) int 4 read bit nmi read bit undefined at read. external interrupt input read register address 95 16
47 m37902fcchp, m37902fgchp, m37902fjchp mitsubishi microcomputers single-chip 16-bit cmos microcomputer fig. 35 bit configuration of interrupt control register 76543210 interrupt priority level select bits (note 1) interrupt request bit 0 : no interrupt requested 1 : interrupt requested 76543210 interrupt priority level select bits (notes 1, 2) interrupt request bit 0 : no interrupt requested 1 : interrupt requested polarity select bit 0 : interrupt request bit is set to 1 at h level when level sense is selected; this bit is set to 1 at falling edge when edge sense is selected. 1 : interrupt request bit is set to 1 at l level when level sense is selected; this bit is set to 1 at rising edge when edge sense is selected. level/edge select bit 0 : edge sense 1 : level sense interrupt control register bit configuration for a-d converter, uart0, uart1, timer a0 to timer a4, and timer b0 to timer b2. interrupt control register bit configuration for int 0 int 2 76543210 interrupt priority level select bits interrupt request bit (note 1) 0 : no interrupt requested 1 : interrupt requested polarity select bit 0 : interrupt request bit is set to 1 at falling edge. 1 : interrupt request bit is set to 1 at rising edge. interrupt control register bit configuration for int 3 and int 4 notes 1: use the movm (movmb) instruction or the sta (stab, stad) instruction for writing to this bit. 2: interrupt request bits of int 0 to int 2 are invalid when the level sense is selected.
m37902fcchp, m37902fgchp, m37902fjchp 48 mitsubishi microcomputers single-chip 16-bit cmos microcomputer interrupts caused by the address matching detection and when di- viding by zero are software interrupts and are not included in figure 36. other interrupts previously mentioned are a-d converter, uart, etc. interrupts. the priority of these interrupts can be changed by chang- ing the priority level in the corresponding interrupt control register by software. figure 37 shows a diagram of the interrupt priority detection circuit when an interrupt is caused, each interrupt device compares its own priority with the priority from above and if its own priority is higher, then it sends the priority below and requests the interrupt. if the pri- orities are the same, the one above has priority. this comparison is repeated to select the interrupt with the highest priority among the interrupts that are being requested. finally the selected interrupt is compared with the processor interrupt priority level (ipl) contained in the processor status register (ps) and the request is accepted if it is higher than ipl and the interrupt disable flag i is 0 . the request is not accepted if flag i is 1 . the reset, nmi, and watchdog timer interrupts are not affected by the interrupt dis- able flag i. when an interrupt is accepted, the contents of the processor status register (ps) is saved to the stack and the interrupt disable flag i is set to 1 . furthermore, the interrupt request bit of the accepted interrupt is cleared to 0 and the processor interrupt priority level (ipl) in the processor status register (ps) is replaced by the priority level of the accepted interrupt. therefore, multi-level priority interrupts are possible by resetting the interrupt disable flag i to 0 and enable further interrupts. for reset, watchdog timer, zero divide, nmi, and address match de- tection interrupts, which do not have an interrupt control register, the processor interrupt level (ipl) is set as shown in table 10. table 9. addresses of interrupt control registers interrupt control registers int 3 interrupt control register int 4 interrupt control register a-d interrupt control register uart0 transmit interrupt control register uart0 receive interrupt control register uart1 transmit interrupt control register uart1 receive interrupt control register timer a0 interrupt control register timer a1 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b0 interrupt control register timer b1 interrupt control register timer b2 interrupt control register int 0 interrupt control register int 1 interrupt control register int 2 interrupt control register addresses 00006e 16 00006f 16 000070 16 000071 16 000072 16 000073 16 000074 16 000075 16 000076 16 000077 16 000078 16 000079 16 00007a 16 00007b 16 00007c 16 00007d 16 00007e 16 00007f 16 the interrupt request bit and the interrupt priority level of each inter- rupt source are sampled and latched at each operation code fetch cycle while f sys is h . however, no sampling pulse is generated until the cycles whose number is selected by software has passed, even if the next operation code fetch cycle is generated. the detection of an interrupt which has the highest priority is performed during that time. fig. 36 interrupt priority fig. 37 interrupt priority detection watchdog timer nmi priority is determined by hardware a-d converter, uart, etc. interrupts priority can be changed by software inside ? . reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ??? reset a-d uart1 transmit uart1 receive uart0 transmit uart0 receive timer b2 timer b1 timer b0 timer a4 timer a3 timer a2 timer a1 timer a0 int 2 nmi watchdog timer ipl interrupt request level 0 interrupt disable flag i int 3 int 1 int 2 int 1 int 0 int 4
49 m37902fcchp, m37902fgchp, m37902fjchp mitsubishi microcomputers single-chip 16-bit cmos microcomputer as shown in figure 38, there are three different interrupt priority de- tection time from which one is selected by software. after the se- lected time has elapsed, the highest priority is determined and is processed after the currently executing instruction has been com- pleted. the time is selected with bits 4 and 5 of the processor mode register 0 (address 5e 16 ) shown in figure 24. table 11 shows the relation- ship between these bits and the number of cycles. after a reset, the processor mode register 0 is initialized to 00 16. therefore, the long- est time is automatically set, however, the shortest time must be se- lected by software. table 10. value loaded in processor interrupt level (ipl) during an interrupt interrupt types reset watchdog timer nmi zero divide address matching detection setting value 0 7 7 not change value of ipl. not change value of ipl. table 11. relationship between interrupt priority detection time select bit and number of cycles priority detection time select bit bit 5 0 0 1 bit 4 0 1 0 7 cycles of f sys 4 cycles of f sys 2 cycles of f sys number of cycles (note) fig. 38 interrupt priority detection time operation code fetch cycle f sys sampling pulse priority detection time select one between 00 to 10 with bits 4 and 5 of processor mode register 0 ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 1 1 0 b5b4 (note) note: this pulse resides when 2 cycles of f sys is selected. note: for system clock f sys , refer to the section on the clock gener- ating circuit.
m37902fcchp, m37902fgchp, m37902fjchp 50 mitsubishi microcomputers single-chip 16-bit cmos microcomputer key input interrupt the int 3 interrupt can function as the key input interrupt by setting bits 1 to 3 of the external interrupt input control register (address 94 16 ). the key input interrupt uses inputs ki 0 to ki 3 . figure 39 shows the block diagram of the int 3 /key input interrupt input circuit, and figure 40 shows the bit configuration of the external interrupt input control register. when bit 0 of the external interrupt input control register (key input interrupt select bit)= 0 , a signal from pin int 3 is connected to the int 3 interrupt control circuit, and int 3 external interrupt is normally performed. when bit 0 = 1 , signals from pins ki 0 to ki 3 , which cor- respond to ports p5 4 to p5 7 pins, are inverted, and then, the logical sum of these signals is connected to the int 3 interrupt control regis- ter. in this case, the external interrupt which uses pins ki 0 to ki 3 is performed. bits 2 and 3 of the external interrupt input control register are the key input interrupt pin select bits. by setting these bits, the combination of key input interrupt pins can be selected. the interrupt vector ad- dresses and interrupt control register of the key input interrupt are common to those of the int 3 interrupt. additionally, pullup resistors (transistors) can be added to pins ki 0 to ki 4 by setting as follows: set bit 1 of the external interrupt input control register to 1 . next, select the key input interrupt pins by bits 2 and 3 of the exter- nal interrupt input control register. then, clear the contents of the port direction register which corre- sponds to the selected pins to 0 . pullup transistor pullup transistor pullup transistor p5 4 /ki 0 port p5 6 direction register key input interrupt pin pullup select bit p5 6 /ki 2 ki 2 enable signal (note) int 3 interrupt request int 3 interrupt control register 0 1 key input interrupt pin pullup select bit p5 7 /ki 3 port p5 7 direction register ki 3 enable signal (note) p5 7 /ki 3 interrupt control circuit note: ki i enable signal (i = 0 to 3) means a signal which becomes 1 when the key input interrupt select bit = 1 and pin ki i is selected by the key input interrupt pin select bits. port p5j direction register : bit j (j = 4 to 7) at address d 16 int 3 interrupt control register : address 6e 16 key input interrupt select bit : bit 0 at address 94 16 key input interrupt pin pullup select bit : bit 1 at address 94 16 pin int 3 select bit : bit 5 at address 94 16 0 1 p7 4 /(int 3 ) p8 0 /int 3 pin int 3 select bit key input interrupt select bit port p5 5 direction register key input interrupt pin pullup select bit p5 5 /ki 1 ki 1 enable signal (note) port p5 4 direction register key input interrupt pin pullup select bit ki 0 enable signal (note) pullup transistor fig. 39 block diagram of int 3 /key input interrupt input circuit
51 m37902fcchp, m37902fgchp, m37902fjchp mitsubishi microcomputers single-chip 16-bit cmos microcomputer fig. 40 bit configuration of external interrupt input control register 76543210 external interrupt input control register key input interrupt select bit 0: int 3 interrupt 1: key input interrupt pin int 2 select bit 0: allocate pin int 2 to p6 4 . 1: allocate pin int 2 to p7 7 (note 2) . key input interrupt pin select bits (note 1) 0 0: pins ki 0 to ki 3 0 1: pins ki 0 to ki 2 1 0: pins ki 0 and ki 1 1 1: pin ki 0 address 94 16 at reset 00 16 key input interrupt pin pullup select bit 0: pins ki 0 to ki 3 are not pulled up. 1: pins ki 0 to ki 3 are pulled up. pin int 3 select bit (note 3) 0: allocate pin int 3 to p8 0 . 1: allocate pin int 3 to p7 4 . pin int 4 select bit 0: allocate pin int 4 to p8 4 . 1: allocate pin int 4 to p7 5 (note 4) . fix this bit to 0 . notes 1: when using pin ki i , do not select timer a s output pins and pulse output pins which are multiplexed with pin ki i . 2: when pin int 2 is allocated to p7 7 , do not use pin an 7 /ad trg . additionally, clear the d-a 1 output enable bit (bit 1 at address 96 16 ) to 0 (output disabled). 3: when pin int 3 is allocated to p8 0 , clear the d-a 2 output enable bit (bit 2 at address 96 16 ) to 0 (output disabled). when pin int 3 is allocated to p7 4 , do not use pin an 4 . 4: when pin int 4 is allocated to p7 5 , do not use pin an 5 . 0
m37902fcchp, m37902fgchp, m37902fjchp 52 mitsubishi microcomputers single-chip 16-bit cmos microcomputer timer there are eight 16-bit timers. they are divided by type into timer a(5) and timer b(3). the timer i/o pins are multiplexed with i/o pins for port p5 and p6. to use these pins as timer input pins, the port direction register bit corresponding to the pin must be cleared to 0 to specify input mode. timer a figure 41 shows a block diagram of timer a. timer a has four modes: timer mode, event counter mode, one-shot pulse mode, and pulse width modulation mode. the mode is se- lected with bits 0 and 1 of the timer ai mode register (i = 0 to 4). each of these modes is described below. figure 42 shows the bit configuration of the timer a clock division se- lect register. timers a0 to a4 use the count source which has been selected by bits 0 and 1 of this register. (1) timer mode [00] figure 43 shows the bit configuration of the timer ai mode register during timer mode. bits 0, 1 and 5 of the timer ai mode register must be 0 in timer mode. the timer a s count source is selected by bits 6 and 7 of the timer ai mode register and the contents of the timer a clock division select register. (see table 12.) the counting of the selected clock starts when the count start bit is 1 and stops when it is 0 . figure 44 shows the bit configuration of the count start bit. the counter is decremented, an interrupt is caused and the interrupt re- quest bit in the timer ai interrupt control register is set when the con- tents becomes 0000 16 . at the same time, the contents of the reload register is transferred to the counter and count is continued. fig. 41 block diagram of timer a timer one-shot pulse pulse width count start register (address 40 16 ) countdown data bus (odd) data bus (even) reload register(16) counter (16) (low-order 8 bits) (high-order 8 bits) countdown is always selected when not in the event counter mode. timer a0 47 16 46 16 timer a1 49 16 48 16 timer a2 4b 16 4a 16 timer a3 4d 16 4c 16 timer a4 4f 16 4e 16 countup/countdown switching toggle flip-flop up-down register (address 44 16 ) polarity selection addresses external trigger event counter tai in (i = 0 4) tai out (i = 0 4) timer (gate function) count source select bits pulse output f 1 f 2 f 16 f 64 f 512 f 4096 timer a clock division select bit
53 m37902fcchp, m37902fgchp, m37902fjchp mitsubishi microcomputers single-chip 16-bit cmos microcomputer when bit 2 of the timer ai mode register is 1 , the output is gener- ated from tai out pin. the output is toggled each time the contents of the counter reaches to 0000 16 . when the contents of the count start bit is 0 , l is output from tai out pin. when bit 2 is 0 , tai out can be used as a normal port pin. when bit 4 is 0 , tai in can be used as a normal port pin. when bit 4 is 1 , counting is performed only while the input signal from the tai in pin is h or l as shown in figure 45. therefore, this can be used to measure the pulse width of the tai in input signal. whether to count while the input signal is h or while it is l is de- termined by bit 3. if bit 3 is 1 , counting is performed while the tai in pin input signal is h and if bit 3 is 0 , counting is performed while it is l . note that, the duration of h or l on the tai in pin must be 2 or more cycles of the timer count source. when data is written to timer ai register with timer ai halted, the same data is also written to the reload register and the counter. when data is written to timer ai which is busy, the data is written to the reload register, but not to the counter. the new data is reloaded from the reload register to the counter at the next reload time and counting continues. the contents of the counter can be read at any time. when the value set in the timer ai register is n, the timer frequency division ratio is 1/(n+1). 0 0 : always 00 in timer mode 0 : no pulse output (tai out is normal port pin.) 1 : pulse output (tai out is pulse output pin.) (note) 0 : no gate function (tai in is normal port pin.) 1 0 : count only while tai in input is l . 1 1 : count only while tai in input is h . 0 : always 0 in timer mode. clock source select bits see table 12. timer a0 mode register timer a1 mode register timer a2 mode register timer a3 mode register timer a4 mode register 7 00 6543210 addresses 56 16 57 16 58 16 59 16 5a 16 0 note: when using pins ta2 out and ta3 out as pulse output pins, do not select pins ki 0 and ki 2 . because they are key input interrupt pins and are multiplexed with pins ta2 out and ta3 out . fig. 43 bit configuration of timer ai mode register during timer mode fig. 42 bit configuration of timer a clock division select register table 12. relationship between timer a clock division select bits, clock source select bits, and count source timer a clock division select bit (see table 12.) 76543210 timer a clock division select register address 45 16 0 at read. clock source select bits (bits 7 and 6 at addresses 56 16 to 5a 16 ) 1 0 0 0 0 1 timer a clock division select bits (bits 1 and 0 at address 45 16 ) f 2 f 16 f 64 1 1 f 512 00 f 1 f 16 f 64 f 4096 01 f 1 f 64 f 512 f 4096 10 11 do not select. note: timers a0 to a4 use the same clock, which is selected by the timer a clock division select bits.
m37902fcchp, m37902fgchp, m37902fjchp 54 mitsubishi microcomputers single-chip 16-bit cmos microcomputer fig. 44 bit configuration of count start register fig. 45 count waveform when gate function is available 76543210 timer a0 count start bit timer a1 count start bit timer a2 count start bit timer a3 count start bit timer a4 count start bit timer b0 count start bit timer b1 count start bit timer b2 count start bit count start register (stop at 0 , start at 1 ) address 40 16 selected clock source fi tai in bit 4 bit 3 10 timer mode register bit 4 bit 3 11 timer mode register
55 m37902fcchp, m37902fgchp, m37902fjchp mitsubishi microcomputers single-chip 16-bit cmos microcomputer (2) event counter mode [01] figure 46 shows the bit configuration of the timer ai mode register during event counter mode. in event counter mode, bit 0 of the timer ai mode register must be 1 and bits 1 and 5 must be 0 . the input signal from the tai in pin is counted when the count start bit shown in figure 44 is 1 and counting is stopped when it is 0 . count is performed at the fall of the input signal when bit 3 is 0 and at the rise of the signal when it is 1 . in event counter mode, whether to increment or decrement the count can be selected with the up-down bit or the input signal from the tai out pin. when bit 4 of the timer ai mode register is 0 , the up-down bit is used to determine whether to increment or decrement the count (decrement when the bit is 0 and increment when it is 1 ). figure 47 shows the bit configuration of the up-down register. when bit 4 of the timer ai mode register is 1 , the input signal from the tai out pin is used to determine whether to increment or decre- ment the count. however, note that bit 2 must be 0 if bit 4 is 1. it is because if bit 2 is 1 , tai out pin becomes an output pin to output pulses. the count is decremented when the input signal from the tai out pin is l and incremented when it is h . determine the level of the input signal from the tai out pin before a valid edge is input to the tai in pin. an interrupt request signal is generated and the interrupt request bit in the timer ai interrupt control register is set when the counter reaches 0000 16 (decrement count) or ffff 16 (increment count). at the same time, the contents of the reload register is transferred to the counter and the count is continued. when bit 2 is 1, each time the counter reaches 0000 16 (decrement count) or ffff 16 (increment count), the waveform s polarity is re- versed and is output from tai out pin. if bit 2 is 0 , tai out pin can be used as a normal port pin. however, if bit 4 is 1 and the tai out pin is used as an output pin, the output from the pin changes the count direction. therefore, bit 4 must be 0 unless the output from the tai out pin is to be used to se- lect the count direction. fig. 46 bit configuration of timer ai mode register during event counter mode fig. 47 bit configuration of up-down register 76543210 1 0 0 0 1 : always 01 in event counter mode 0 : no pulse output 1 : pulse output 0 : count at the falling edge of input signal 1 : count at the rising edge of input signal 0 : increment or decrement according to up/down bit 1 : increment or decrement according to tai out pin input signal level 0 : always 0 in event counter mode : not used in event counter mode timer a0 mode register timer a1 mode register timer a2 mode register timer a3 mode register timer a4 mode register addresses 56 16 57 16 58 16 59 16 5a 16 note: when using pins ta2 out and ta3 out as pulse output pins, do not select pins ki 0 and ki 2 . because they are key input interrupt pins and are multiplexed with pins ta2 out and ta3 out . timer a0 up-down bit timer a1 up-down bit timer a2 up-down bit timer a3 up-down bit timer a4 up-down bit timer a2 two-phase pulse signal processing select bit 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing mode timer a3 two-phase pulse signal processing select bit 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing mode timer a4 two-phase pulse signal processing select bit 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing mode up-down register 76543210 address 44 16
m37902fcchp, m37902fgchp, m37902fjchp 56 mitsubishi microcomputers single-chip 16-bit cmos microcomputer nored. (see figure 50.) note that bits 5, 6, and 7 of the up-down reg- ister (address 44 16 ) are the two-phase pulse signal processing se- lect bits for timers a2, a3 and a4 respectively. each timer operates in normal event counter mode when the corresponding bit is 0 and performs two-phase pulse signal processing when it is 1 . count is started by setting the count start bit to 1 . data write and read are performed in the same way as for normal event counter mode. note that the direction register of the input port must be set to input mode because two kinds of pulse signals, described above, are input. also, there can be no pulse output in this mode. data write and data read are performed in the same way as for timer mode. that is, when data is written to timer ai halted, it is also writ- ten to the reload register and the counter. when data is written to timer ai which is busy, the data is written to the reload register, but not to the counter. the counter is reloaded with new data from the reload register at the next reload time. the counter can be read at any time. in event counter mode, whether to increment or decrement the counter can also be determined by supplying two kinds of pulses of which phases differ by 90 to timer a2, a3, or a4. there are two types of two-phase pulse processing operations. one uses timers a2 and a3, and the other uses timer a4. in both processing operations, two pulses described above are input to the ta jout (j = 2 to 4) pin and taj in pin respectively. when timers a2 and a3 are used, as shown in figure 48, the count is incremented when a rising edge is input to the tak in pin after the level of tak out (k=2, 3) pin changes from l to h , and when the falling edge is input, the count is decremented. for timer a4, as shown in figure 49, when a phase-related pulse with a rising edge input to the ta4 in pin is input after the level of ta4 out pin changes from l to h , the count is incremented at the respective rising edge and falling edge of the ta4 out pin and ta4 in pin. when a phase-related pulse with a falling edge input to the ta4 out pin is input after the level of ta4 in pin changes from h to l , the count is decremented at the respective rising edge and falling edge of the ta4 in pin and ta4 out pin. when performing this two-phase pulse signal processing, timer aj mode register bit 0 and bit 4 must be set to 1 and bits 1, 2, 3, and 5 must be 0 . bits 6 and 7 are ig- fig. 50 bit configuration of timer aj mode register when performing two-phase pulse signal processing in event counter mode fig. 48 two-phase pulse processing operation of timers a2 and a3 fig. 49 two-phase pulse processing operation of timer a4 76543210 1 0 0 0 1 0 0 1 : always 01 in event counter mode 0 1 0 0 : always 0100 when processing two-phase pulse signal : not used in event counter mode timer a2 mode register timer a3 mode register timer a4 mode register addresses 58 16 59 16 5a 16 tak out tak in (k = 2, 3) increment- count increment- count increment- count decrement- count decrement- count decrement- count ta4 out ta4 in decrement-count at each edge increment-count at each edge ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? decrement-count at each edge increment-count at each edge ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
57 m37902fcchp, m37902fgchp, m37902fjchp mitsubishi microcomputers single-chip 16-bit cmos microcomputer (3) one-shot pulse mode [10] figure 51 shows the bit configuration of the timer ai mode register during one-shot pulse mode. in one-shot pulse mode, bit 0 and bit 5 must be 0 and bit 1 and bit 2 must be 1 . the trigger is enabled when the count start bit is 1 . the trigger can be generated by software or it can be input from the tai in pin. soft- ware trigger is selected when bit 4 is 0 and the input signal from the tai in pin is used as the trigger when it is 1 . bit 3 is used to determine whether to trigger at the fall of the trigger signal or at the rise. the trigger is at the fall of the trigger signal when bit 3 is 0 and at the rise of the trigger signal when it is 1 . software trigger is generated by setting 1 to a bit in the one-shot start register. each bit corresponds to each timer. figure 52 shows the bit configuration of the one-shot start register. as shown in figure 53, when a trigger signal is received, the counter counts the clock selected by bits 6 and 7 and the contents of the timer a clock division select register. (set table 12.) if the contents of the counter is not 0000 16 , the tai out pin goes h when a trigger signal is received. the count direction is decrement. when the counter reaches 0001 16 , the tai out pin goes l and count is stopped. the contents of the reload register is transferred to the counter. at the same time, an interrupt request signal is gener- ated and the interrupt request bit in the timer ai interrupt control reg- ister is set. this is repeated each time a trigger signal is received. the output pulse width is if the count start flag is 0 , tai out goes l . therefore, the value cor- responding to the desired pulse width must be written to timer ai be- fore setting the timer ai count start bit. as shown in figure 54, a trigger signal can be received before the operation for the previous trigger signal is completed. in this case, the contents of the reload register is transferred to the counter by the trigger and then that value is decremented. except when retriggering while operating, the contents of the reload register are not transferred to the counter by triggering. when retriggering, there must be at least one timer count source cycle before a new trigger can be issued. data write is performed in the same way as for timer mode. when data is written in timer ai halted, it is also written to the reload register and the counter. when data is written to timer ai which is busy, the data is written to the reload register, but not to the counter. the counter is reloaded with new data from the reload register at the next reload time. undefined data is read when timer ai is read. 1 pulse frequency of the selected clock (counter s value at the time of trigger). fig. 51 bit configuration of timer ai mode register during one-shot pulse mode fig. 52 bit configuration of one-shot start register 76543210 0 1 1 0 1 0 : always 10 in one-shot pulse mode 1 : always 1 in one-shot pulse mode 0 : software trigger 1 0 : trigger at the falling edge of tai in input 1 1 : trigger at the rising edge of tai in input 0 : always 0 in one-shot pulse mode clock source select bits (see table 12.) timer a0 mode register timer a1 mode register timer a2 mode register timer a3 mode register timer a4 mode register addresses 56 16 57 16 58 16 59 16 5a 16 76543210 timer a0 one-shot start bit timer a1 one-shot start bit timer a2 one-shot start bit timer a3 one-shot start bit timer a4 one-shot start bit must be fixed to 0 . one-shot start register address 42 16 0
m37902fcchp, m37902fgchp, m37902fjchp 58 mitsubishi microcomputers single-chip 16-bit cmos microcomputer fig. 53 pulse output example when external rising edge is selected fig. 54 example when trigger is re-issued during pulse output selected clock source fi tai in (rising edge) tai out example when the contents of the reload register is 0003 16 selected clock source fi tai in (rising edge) tai out example when the contents of the reload register is 0004 16
59 m37902fcchp, m37902fgchp, m37902fjchp mitsubishi microcomputers single-chip 16-bit cmos microcomputer (4) pulse width modulation mode [11] figure 55 shows the bit configuration of the timer ai mode register during pulse width modulation mode. in pulse width modulation mode, bits 0, 1, and 2 must be set to 1 . bit 5 is used to determine whether to perform 16-bit length pulse width modulator or 8-bit length pulse width modulator. 16-bit length pulse width modulator is selected when bit 5 is 0 and 8-bit length pulse width modulator is selected when it is 1 . the 16-bit length pulse width modulator is described first. the pulse width modulator can be started with a software trigger or with an input signal from a tai in pin (external trigger). the software trigger mode is selected when bit 4 is 0 . pulse width modulator is started and a pulse is output from tai out when the count start bit is set to 1 . the external trigger mode is selected when bit 4 is 1 . pulse width modulation starts when a trigger signal is input from the tai in pin when the count start bit is 1 . whether to trigger at the fall or rise of the trigger signal is determined by bit 3. the trigger is at the fall of the trigger signal when bit 3 is 0 and at the rise when it is 1 . when data is written to timer ai with the pulse width modulator halted, it is written to the reload register and the counter. then when the count start bit is set to 1 and a software trigger or an external trigger is issued to start modulation, the waveform shown in figure 56 is output continuously. once modulation is started, triggers are not accepted. if the value in the reload register is m, the duration h of pulse is m and the output pulse period is (2 16 1). an interrupt request signal is generated and the interrupt request bit in the timer ai interrupt control register is set at each fall of the output pulse. the width of the output pulse is changed by updating timer data. the update can be performed at any time. the output pulse width is changed at the rise of the pulse after data is written to the timer. the contents of the reload register are transferred to the counter just before the rise of the next pulse so that the pulse width is changed from the next output pulse. undefined data is read when timer ai is read. the 8-bit length pulse width modulator is described next. the 8-bit length pulse width modulator is selected when the timer ai mode register bit 5 is 1 . the reload register and the counter are both divided into 8-bit halves. 1 selected clock frequency 1 selected clock frequency the low-order 8 bits function as a prescaler and the high-order 8 bits function as the 8-bit length pulse width modulator. the prescaler counts the clock selected by bits 6, 7, and the contents of the timer a clock division select register. (see table 12.) a pulse is generated when the counter reaches 0000 16 as shown in figure 57. at the same time, the contents of the reload register is transferred to the counter and count is continued. fig. 55 bit configuration of timer ai mode register during pulse width modulation mode 76543210 1 1 1 1 1 : always 11 in pulse width modulation mode 1 : always 1 in pulse width modulation mode 0 : software trigger 1 0 : trigger at the falling of tai in input 1 1 : trigger at the rising of tai in input 0 : 16-bit pulse width modulator 1 : 8-bit pulse width modulator clock source select bits (see table 12.) timer a0 mode register timer a1 mode register timer a2 mode register timer a3 mode register timer a4 mode register addresses 56 16 57 16 58 16 59 16 5a 16
m37902fcchp, m37902fgchp, m37902fjchp 60 mitsubishi microcomputers single-chip 16-bit cmos microcomputer high-order 8 bits of the reload register are m, the duration h of pulse is and the output pulse period is 1 selected clock frequency therefore, if the low-order 8 bits of the reload register are n, the pe- riod of the generated pulse is (n+1). the high-order 8 bits function as an 8-bit length pulse width modula- tor using this pulse as input. the operation is the same as for 16-bit length pulse width modulator except that the length is 8 bits. if the 1 selected clock frequency 1 selected clock frequency fig. 56 16-bit length pulse width modulator output pulse example fig. 57 8-bit length pulse width modulator output pulse example selected clock source fi tai in (rising edge) tai out 1/fi (2 16 1) 1/fi (m) this trigger is not accepted example when the contents of the reload register is 0003 16 selected clock source fi tai in (falling edge) prescaler output (when n = 2) 8-bit length pulse width modulator output (when m = 2) 1/fi (n + 1) (2 8 1) 1/fi (n + 1) (m) 1/fi (n + 1) (n+1) m. (n+1) (2 8 1).
61 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers timer b figure 58 shows a block diagram of timer b. timer b has three modes: timer mode, event counter mode, and pulse period measurement/pulse width measurement mode. the mode is selected with bits 0 and 1 of the timer bi mode register (i=0 to 2). each of these modes is described below. (1) timer mode [00] figure 59 shows the bit configuration of the timer bi mode register during timer mode. bits 0 and 1 of the timer bi mode register must always be ??in timer mode. bits 6 and 7 are used to select the clock source. the counting of the selected clock starts when the count start bit is ??and stops when ?? as shown in figure 44, the timer bi count start bit is at the same ad- dress as the timer ai count start bit. the count is decremented, an interrupt occurs, and the interrupt request bit in the timer bi interrupt control register is set when the contents becomes 0000 16 . at the same time, the contents of the reload register is stored in the counter and count is continued. timer bi does not have a pulse output function or a gate function like timer a. when data is written to timer bi halted, it is written to the reload reg- ister and the counter. when data is written to timer bi which is busy, the data is written to the reload register, but not to the counter. the new data is reloaded from the reload register to the counter at the next reload time and counting continues. the contents of the counter can be read at any time. fig. 58 block diagram of timer b data bus (odd) data bus (even) reload register (16) counter (16) count start register event counter mode notes 1: perform a write and read to/from timer bi register in the condition of 16-bit data length : data length flag (m) = 0 . 2: only for timer b2, a count source in the event counter mode can be selected. (address 40 16 ) counter reset circuit timer mode pulse period measurement/pulse width measurement mode (low-order 8 bits) (high-order 8 bits) f 2 f 16 f 64 f 512 count source select bits fx 32 polarity selection and edge pulse generator tbi in timer b2 clock source select bit (note 2) timer b2 clock source select bit : bit 6 at address 63 16 addresses timer b0 51 16 50 16 timer b1 53 16 52 16 timer b2 55 16 54 16
62 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers (2) event counter mode [01] figure 60 shows the bit configuration of the timer bi mode register during event counter mode. in event counter mode, bit 0 in the timer bi mode register must be 1 and bit 1 must be 0 . the input signal from the tbi in pin is counted when the count start bit is 1 and counting is stopped when it is 0 . count is performed at the fall of the input signal when bits 2, and 3 are 0 and at the rise of the input signal when bit 3 is 0 and bit 2 is 1 . when bit 3 is 1 and bit 2 is 0 , count is performed at the rise and fall of the input signal. data write, data read and timer interrupt are performed in the same way as for timer mode. only for timer b2, when the timer b2 clock source select bit of the particular function select register 1 (bit 6 at address 63 16 ) = 1 in the event counter mode, fx 32 can be selected. (when this bit is 0 , an input signal from pin tb2 in becomes the count source as described above.) for the bit configuration of the particular function select reg- ister 1, refer to the section on the standby function. note: fx 32 = f(x in )/32 (3) pulse period measurement/pulse width measurement mode [10] figure 61 shows the bit configuration of the timer bi mode register during pulse period measurement/pulse width measurement mode. in pulse period measurement/pulse width measurement mode, bit 0 must be 0 and bit 1 must be 1 . bits 6 and 7 are used to select the clock source. the selected clock is counted when the count start bit is 1 and counting stops when it is 0 . the pulse period measurement mode is selected when bit 3 is 0 . in pulse period measurement mode, the selected clock is counted dur- ing the interval starting at the fall of the input signal from the tbi in pin to the next fall or at the rise of the input signal to the next rise; the result is stored in the reload register. in this case, the reload register acts as a buffer register. when bit 2 is 0 , the clock is counted from the fall of the input signal to the next fall. when bit 2 is 1 , the clock is counted from the rise of the input signal to the next rise. in the case of counting from the fall of the input signal to the next fall, counting is performed as follows. as shown in figure 62, when the fall of the input signal from tbi in pin is detected, the contents of the counter is transferred to the reload register. next, the counter is cleared and count is started from the next clock. when the fall of the next input signal is detected, the contents of the counter is trans- ferred to the reload register once more, the counter is cleared, and the count is started. the period from the fall of the input signal to the next fall is measured in this way. after the contents of the counter is transferred to the reload register, an interrupt request signal is generated and the interrupt request bit in the timer bi interrupt control register is set. however, no interrupt request signal is generated when the contents of the counter is trans- ferred first to the reload register after the count start bit is set to 1 . when bit 3 is 1 , the pulse width measurement mode is selected. pulse width measurement mode is the same as the pulse period measurement mode except that the clock is counted from the fall of the tbi in pin input signal to the next rise or from the rise of the input signal to the next fall as shown in figure 63. fig. 59 bit configuration of timer bi mode register during timer mode fig. 60 bit configuration of timer bi mode register during event counter mode fig. 61 bit configuration of timer bi mode register during pulse period measurement/pulse width measurement mode 0 0 : always 00 in timer mode : not used in timer mode and may be any not used in timer mode clock source select bits 0 0 : select f 2 0 1 : select f 16 1 0 : select f 64 1 1 : select f 512 76543210 0 0 timer b0 mode register timer b1 mode register timer b2 mode register addresses 5b 16 5c 16 5d 16 0 1 : always 01 in event counter mode 0 0 : count at the falling edge of input signal 0 1 : count at the rising edge of input signal 1 0 : count at the both falling edge and rising edge of input signal : not used in event counter mode 76543210 1 0 timer b0 mode register timer b1 mode register timer b2 mode register addresses 5b 16 5c 16 5d 16 1 0 : always 10 in pulse period measurement/pulse width measurement mode 0 0 : count from the falling edge of input signal to the next falling one 0 1 : count from the rising edge of input signal to the next rising one 1 0 : count from the falling edge of input signal to the next rising one and from the rising edge to the next falling one timer bi overflow flag clock source select bits 0 0 : select f 2 0 1 : select f 16 1 0 : select f 64 1 1 : select f 512 76543210 0 1 timer b0 mode register timer b1 mode register timer b2 mode register addresses 5b 16 5c 16 5d 16
63 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers when timer bi is read, the contents of the reload register is read. note that in this mode, the interval between the fall of the tbi in pin input signal to the next rise or from the rise to the next fall must be at least two cycles of the timer count source. timer bi overflow flag which is bit 5 of timer bi mode register is set to 1 when the timer bi counter reaches 0000 16 , which indicates that a pulse width or pulse period is longer than that which can be mea- sured by a 16-bit length. this flag is cleared by writing data to the corresponding timer bi mode register. this flag is set to 1 at reset. fig. 62 pulse period measurement mode operation (example of measuring the interval between the falling edge to next falling one ) fig. 63 pulse width measurement mode operation selected clock source fi tbi in reload register counter counter 0 count start bit interrupt request signal selected clock source fi tbi in reload register counter counter 0 count start bit interrupt request signal
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 64 serial i/o mode select bits 0 0 0 : serial i/o is invalid. (port p8 functions as a programmable i/o port.) 0 0 1 : clock synchronous 1 0 0 : 7-bit uart 1 0 1 : 8-bit uart 1 1 0 : 9-bit uart internal/external clock select bit 0 : internal clock 1 : external clock stop bit length select bit (valid in uart mode.) 0 : 1 stop bit 1 : 2 stop bits odd/even parity select bit (valid in uart mode with the parity enable bit = ??) (note) 0 : odd parity 1 : even parity parity enable bit (valid in uart mode) (note) 0 : no parity 1 : with parity sleep select bit (valid in uart mode) (note) 0 : no sleep 1 : sleep 76543210 uart 0 transmit/receive mode register uart 1 transmit/receive mode register addresses 30 16 38 16 note: in the clock synchronous serial i/o mode, bits 4 to 6 are invalid. (each of them may be ??or ??) furthermore, fix bit 7 to ?? serial i/o ports two independent serial i/o ports are provided. figure 64 shows a block diagram of the serial i/o ports. bits 0 to 2 of the uarti(i = 0,1) transmit/receive mode register shown in figure 65 are used to determine whether to use port p8 as a programmable i/o port, clock synchronous serial i/o port, or asyn- chronous (uart) serial i/o port which uses start and stop bits. figures 66 and 67 show the block diagrams of the receiver/transmit- ter . figure 68 shows the bit configuration of the uarti transmit/receive control register. each communication method is described below. fig. 65 bit configuration of uarti transmit/receive mode register fig. 64 block diagram of serial i/o port uarti receive register t x d i r x d i receive control circuit transmit control circuit uarti transmit register 1/16 divider 1/2 divider 1/(n + 1) divider 1/16 divider transfer clock transfer clock uarti transmit buffer register uart clock synchronous clock synchronous clock synchronous (when internal clock selected) brg count source select bits f 2 f 16 f 64 f 512 clock synchronous (internal clock) uart d 7 d 6 d 5 d 4 d 3 d 2 d 1 uarti receive buffer register d 0 d 7 d 8 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0d 8 0 0 0 0 0 0 brgi uart0 (addresses 33 16 , 32 16 ) uart1 (addresses 3b 16 , 3a 16 ) uart0 (addresses 37 16, 36 16 ) uart1 (addresses 3f 16 , 3e 16 ) cts i /rts i clock synchronous (external clock) n = a value set into the uarti baud rate register (brgi) clk i cts i cts i /clk i data bus (even) data bus (odd) bit converter data bus (odd) data bus (even) bit converter
65 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers data bus (odd) data bus (even) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 sp sp par no parity uarti receive register r x d i uarti receive buffer register 9-bit uart 7-bit uart 7-bit uart 8-bit uart synchronous uart 8-bit uart 9-bit uart synchronous synchronous parity 2sp 1sp 0 0 0 0 0 0 0 sp : stop bit par : parity bit fig. 66 block diagram of receiver fig. 67 block diagram of transmitter d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 sp par t x d i 2sp sp 1sp uart 0 data bus (odd) data bus (even) no parity 7-bit uart 9-bit uart synchronous 7-bit uart 8-bit uart 9-bit uart synchronous 8-bit uart synchronous parity sp : stop bit par : parity bit uarti transmit register uarti receive transmit register
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 66 fig. 68 bit configuration of uarti transmit/receive control register /lsb msb t x epty 76543210 r/c cs 1 cs 0 brg count source select bits 0 0 : f 2 0 1 : f 16 1 0 : f 64 1 1 : f 512 cts/rts function select bit (note 1) 0 : cts function is selected. 1 : rts function is selected. transmit register empty flag 0 : data is present in the transmit register. (transmission is in progress.) 1 : no data is present in the transmit register. (transmission is completed.) cts/rts enable bit 0 : cts, rts function is enabled. 1 : cts, rts function is disabled. uarti receive interrupt mode select bit 0 : reception interrupt 1 : reception error interrupt clk polarity select bit (this bit is used in the clock synchronous serial i/o mode.) (note 2) 0 : at the falling edge of a transfer clock, transmit data is output; at the rising edge, receive data is input. when not in transfer, pin clk s level is h . 1 : at the rising edge of a transfer clock, transmit data is output; at the falling edge, receive data is input. when not in transfer, pin clk s level is l . transfer format select bit (this bit is used in the clock synchronous serial i/o mode.) (note 2) 0 : lsb (least significant bit) first 1 : msb (most significant bit) first 76543210 re ri oer fer per sum ti te transmit enable bit transmit buffer empty flag receive enable bit receive complete flag overrun error flag framing error flag (note 3) parity error flag (note 3) error sum flag (note 3) uart0 transmit/receive control register 0 uart1 transmit/receive control register 0 address 34 16 3c 16 uart0 transmit/receive control register 1 uart1 transmit/receive control register 1 address 35 16 3d 16 cpl notes 1: valid when the cts/rts enable bit (bit 4) = 0 . 2: fix these bits to 0 in uart mode or when serial i/o is invalid. 3: valid in uart mode.
67 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers clock synchronous serial communi- cation a case where communication is performed between two clock syn- chronous serial i/o ports as shown in figure 69 will be described. (the transmission side will be denoted by subscript j and the receiv- ing side will be denoted by subscript k.) bit 0 of the uartj transmit/receive mode register and uartk trans- mit/receive mode register must be set to 1 and bits 1 and 2 must be 0 . the length of the transmission data is fixed at 8 bits. bit 3 of the uartj transmit/receive mode register of the clock send- ing side is cleared to 0 to select the internal clock. bit 3 of the uartk transmit/receive mode register of the clock receiving side is set to 1 to select the external clock. bits 4, 5 and 6 are ignored in clock synchronous mode. bit 7 must always be 0 . the clock source is selected by bit 0 (cs 0 ) and bit 1 (cs 1 ) of the clock-sending-side uartj transmit/receive control register 0. as shown in figure 64, the selected clock is divided by (n+1), then by 2, is passed through a transmission control circuit, and is output as transmission clock clkj. therefore, when the selected clock is fi, bit rate = f i / {(n + 1) 0 when _______ _______ _______ _______ cts or rts signal is used. bit 4 must be 1 when cts and rts sig- _______ _______ _______ nals are not used. when cts and rts signals are not used, cts/ _______ rts pin can be used as a normal port pin. _______ _______ when using pin cts/rts, : if bit 2 of the uarti transmit/receive control register 0 is cleared to _______ 0 , cts input is selected. _______ if bit 2 is set to 1 , rts output is selected. _______ _______ the case using cts and rts signals are explained below. as shown in figure 76, bits 2 and 3 of the serial i/o pin control register can determine whether port pins p8 3 and p8 7 are used as pins txdi or as port pins. when bits 2 and 3 are 0 , p8 3 and p8 7 function as pins txdi; when bits 2 and 3 are 1 , p8 3 and p8 7 function as port pins. therefore, in the input-only system where pins txdi are not used, pins txdi can function as port pins. fig. 69 clock synchronous serial communication uartj transmit register txdj rxdj clkj ctsj uartj transmit buffer register uartj receive buffer register uartj receive register uartj transmit/receive mode register uartj transmit/receive control register 0 uartj transmit/receive control register 1 000 0 t x epty cs 1 cs 0 re ri oer fer per cpl cpl sum ti te 0 uartk transmit register uartk transmit buffer register uartk receive buffer register uartk receive register uartk transmit/receive mode register uartk transmit/receive control register 0 uartk transmit/receive control register 1 011 0 1 t x epty msb /lsb re ri oer fer per sum ti te 0 1 txdk rxdk clkk rtsk msb /lsb
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 68 transmission transmission is started when bit 0 (tej flag: transmit enable bit) of uartj transmit/receive control register 1 is 1 , bit 1 (tij flag) of one ________ is 0 , and ctsj input is l . the tij flag indicates whether the trans- mit buffer register is empty or not. it is cleared to 0 when data is written in the transmit buffer register ; it is set to 1 when the con- tents of the transmit buffer register is transferred to the transmit reg- ister and the transmit buffer register becomes empty. when all of the transmit conditions are satisfied, the transmit data in the transmit buffer register are transferred to the transmit register, and transmission starts. as shown in figure 70, data is output from t x dj pin each time when transmission clock clkj changes from h to l . (in the clock synchronous serial i/o mode, the polarity of a transfer clock can be changed. for details, refer to the section on the selection of the transfer clock polarity.) the data is output from the least significant bit. when the transmit register becomes empty after the contents has been transmitted, data is transferred automatically from the transmit buffer register to the transmit register if the next transmission start condition is satisfied. the next transmission is performed succeedingly. once transmission has started, the tej flag, tij flag, and ctsj signals are ignored until data transmission completes. ________ therefore, transmission is not interrupt when ctsj input is changed to h during transmission. the transmission start condition indicated by tej flag, tij flag, and ________ ctsj is checked while the t end j signal (shown in figure 70) is h . therefore, data can be transmitted continuously if the next transmis- sion data is written in the transmit buffer register and tij flag is cleared to 0 before thet end j signal goes h . bit 3 (t x eptyj flag) of uartj transmit/receive control register 0 changes to 1 at the next cycle just after the t end j signal goes h and changes to 0 when transmission starts. therefore, this flag can be used to determine whether data transmission has completed. when the tij flag changes from 0 to 1 , the interrupt request bit in the uartj transmit interrupt control register is set to 1 . receive when bit 2 of the uart k transmit/receive control register 1 is set to 1 , reception becomes enabled. in this case, when the clkk signal is input, the receive operation starts simultaneously with this signal. __________ the rtsk output is h when the rek flag is 0 . when the rek flag __________ is set to 1 , the rtsk output becomes l . this informs the transmit- ter side that reception becomes enabled. when the receive opera- __________ tion starts, the rtsk output automatically becomes h . when the receive operation starts, the receiver takes data from pin rxdk each time when the transmit clock (clkj) turns from l to h . simultaneously with reception, the contents of the receiver register is shifted bit by bit. (note that, in the clock synchronous serial communication, the polar- ity of a transfer clock can be inverted. for details, refer to the section on the polarity of the transfer clock.) when an 8-bit data is received, the contents of the receive register is transferred to the receive buffer register and bit 3 (rik flag) of uartk transmit/receive control regis- ter 1 is set to 1 . in other words, the setting 1 to the rik flag indi- cates that the receive buffer register contains the received data. at this time, if the low-order byte of the uartk receive buffer register is _____ read out, the rtsk output turns back to l . this indicates that the next data reception becomes enabled. bit 4 (oerk flag) of uartk transmit/receive control register 1 is set to 1 when the next data is transferred from the receive register to the receive buffer register while rik flag is 1 , and indicates that the next data was transferred to the receive register before the contents of the receive buffer regis- ter was read. (in other words, this indicates that an overrun error has occurred.) rik flag is automatically cleared to 0 when the low-order byte of the receive buffer register is read or when the rek flag is cleared to 0 . the oerk flag is cleared when the rek flag is cleared. bit 5 (ferk flag), bit 6 (perk flag), and bit 7 (sumk flag) are ignored in clock synchronous mode. as shown in figure 64, with clock synchronous serial communica- tion, data cannot be received unless the transmitter is operating be- cause the receive clock is created from the transmission clock. therefore, the transmitter must be operating even when there is no need to sent data from uartk to uartj.
69 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers transmission clock te j 1/f i + + 0 clk j t endj t x d j t x epty j fig. 70 clock synchronous serial i/o timing interrupt request at completion of reception when the rik flag changes from 0 to 1 , in other words, when the receive operation is completed, the interrupt request bit of the uartk receive interrupt control register can be set to 1 . the timing when this interrupt request bit is to be set to 1 can be selected from the following: each reception when an error occurs at reception if bit 5 of the uartk transmit/receive control register 0 (uart re- ceive interrupt mode select bit) is cleared to 0 , the interrupt request bit is set to 1 at each reception. if bit 5 is set to 1 , the interrupt re- quest bit is set to 1 only when an error occurs. (in the clock syn- chronous serial communication, only when an overrun error occurs, the interrupt request bit is set to 1 .) polarity of transfer clock in the clock synchronous serial communication, by bit 6 of the uartj transmit/receive control register 0 (cpl), the polarity of a transfer clock can be selected. as shown in figure 71, when bit 6 = 0 , the polarity is as follows: in transmission, transmit data is output at the falling edge of clkj. in reception, receive data is input at the rising edge of clkk. when not in transfer, clki is at h level. when bit 6 = 1 , the polarity is as follows: in transmission, transmit data is output at the rising edge of clkj. in reception, receive data is input at the rising edge of clkk. when not in transfer, clki is at l level.
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 70 fig. 71 polarity of transfer clock ? s level is h . ? s level is l .
71 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers selection of transfer format in clock synchronous serial communication, transfer format can be selected by bit 7 of the transmit/receive control register 0. when bit 7 is 0 , transfer format is lsb first. when bit 7 is 1 , transfer format is msb first. this function is realized by changing connection relation between the transmit buffer register and the receive buffer register when writ- ing transmit data to the transmit buffer register or reading receive data from the receive buffer register. accordingly, the transmitter s operation is the same in both transfer formats. figure 72 shows the connection relation. fig. 72 connection relation between transmit buffer register, receive buffer register, and data bus bit 7 in transmit/receive control register 0 write to transmit buffer register read from receive buffer register 0 (lsb first) 1 (msb first) transmit buffer register db 7 data bus d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 db 6 db 5 db 4 db 3 db 2 db 1 db 0 transmit buffer register db 7 data bus d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 db 6 db 5 db 4 db 3 db 2 db 1 db 0 receive buffer register db 7 data bus d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 db 6 db 5 db 4 db 3 db 2 db 1 db 0 receive buffer register db 7 data bus d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 db 6 db 5 db 4 db 3 db 2 db 1 db 0 precautions for clock synchronous serial communication ________ ________ when using pin cts 0 /rts 0 , be sure to clear the d-a 2 output enable bit (bit 2 at address 96 16 ) to 0 (output disabled). also, in the clock _______ synchronous serial communication, the separate function for ctsi/ _______ rtsi cannot be selected. furthermore, when an internal clock is se- _______ _______ lected, rts output is undefined. therefore, do not use the rts func- tion. before transmit operation is performed, be sure to clear bits 2 and 3 of the serial i/o pin control register (address ac 16 ) to 00 .
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 72 fig. 73 transmit timing example when 8-bit asynchronous communication with parity and 1 stop bit selected fig. 74 transmit timing example when 9-bit asynchronous communication with no parity and 2 stop bits selected asynchronous serial communication asynchronous serial communication can be performed using 7-, 8-, or 9-bit length data. the operation is the same for all data lengths. the following is the description for 8-bit asynchronous communication. with 8-bit asynchronous communication, bit 0 of uarti transmit/re- ceive mode register is 1 , bit 1 is 0 , and bit 2 is 1 . bit 3 is used to select an internal clock or an external clock. if bit 3 is 0 , an internal clock is selected and if bit 3 is 1 , then external clock is selected. if an internal clock is selected, bit 0 (cs 0 ) and bit 1 (cs 1 ) of uarti transmit/receive control register 0 are used to select the clock source. when an internal clock is selected for asynchronous serial communication, the clki pin can be used as a normal i/o pin. the selected internal or external clock is divided by (n+1), then by 16, and is passed through a control circuit to create the uart trans- mission clock or uart receive clock. therefore, the transmission speed can be changed by changing the contents (n) of the bit rate generator. if the selected clock is an inter- nal clock pfi or an external clock f ext , bit rate = (fi or f ext ) / {(n+1) 11 , the above separation is per- formed. when bits 0 and 1 = 00 , no separation is performed. _______ _______ table 13 lists the selection methods of the cts/rts function. (1/f i or 1/f ext ) + 0 (1/f i or 1/f ext ) + 0 start bit stop bit stop bit
73 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers ________ once transmission has started, the tei flag, tii flag, and ctsi signal are ignored until data transmission is completed. therefore, transmission does not stop until it completes event if, dur- ing transmission, the tei flag is cleared to 0 or ctsi input is set to 1 . the transmission start condition indicated by tei flag, tii flag, and ________ ctsi is checked while the t end i signal shown in figure 73 is h . therefore, data can be transmitted continuously if the next transmis- sion data is written in the transmit buffer register and tii flag is cleared to 0 before the t end i signal goes h . bit 3 (t x eptyi flag) of uarti transmit/receive control register 0 changes to 1 at the next cycle just after the t end i signal goes h and changes to 0 when transmission starts. therefore, this flag can be used to determine whether data transmission is completed. when the tii flag changes from 0 to 1 , the interrupt request bit of the uarti transmit interrupt control register is set to 1 . transmission transmission is started when bit 0 (tei flag transmit enable flag) of uarti transmit/receive control register 1 is 1 , bit 1 (tii flag) is 0 , ________ and ctsi input (in other words, transmit enable signal input from re- ceiver) is l. the tii flag indicates whether the transmit buffer is empty or not. it is cleared to 0 when data is written in the transmit buffer; it is set to 1 when the contents of the transmit buffer register is transferred to the transmit register. when all of the transmission conditions are satisfied, transmit data is transferred to the transmit register, and transmit operation starts. as shown in figures 73 and 74, data is output from the t x di pin with the stop bit or parity bit specified by bits 4 to 6 of uarti transmit/re- ceive mode register. the data is output from the least significant bit. when the transmit register becomes empty after the contents has been transmitted, data is transferred automatically from the transmit buffer register to the transmit register if the next transmit start condi- tion is satisfied. then, the next transmission is performed succeedingly. fig. 75 receive timing example when 8-bit asynchronous communication with no parity and 1 stop bit selected start bit stop bit start bit d 0 d 1 d 7 check to be l level starting at the falling edge of start bit data fetched f i or f ext re i r x d i receive clock ri i rts i
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 74 table 13. selection methods of cts/rts function cts i /rts i separate select bit ? ? (notes 2 and 3) p8 1 or clk 0 pin p8 4 /cts 1 /rts 1 pin p8 5 /cts 1 /clk 1 notes 1: when using the cts 0 /rts 0 pin, be sure to clear the d-a 2 output enable bit (bit 2 at address 96 16 ) to 0 . 2: when using the cts function, be sure to clear the corresponding bit of the port p8 direction register to 0 . 3: when ctsi and rtsi has been separated, the clki pin cannot be used. therefore, in the clock synchronous serial communication, ctsi and rtsi cannot be separated. also, when ctsi and rtsi are separated in uart mode, be sure to select an internal clock. cts/rts function select bit cts/rts enable bit ? (note 1) cts 1 rts 1 rts 1 p8 4 p8 5 or clk 1 p8 5 or clk 1 cts 1 (notes 2 and 3) p8 5 or clk 1 ? 0 or 1 . fig. 76 bit configuration of serial i/o pin control register cts 0 /rts 0 separate select bit 0 : cts 0 /rts 0 are used together. 1 : cts 0 /rts 0 are separated. cts 1 /rts 1 separate select bit 0 : cts 1 /rts 1 are used together. 1 : cts 1 /rts 1 are separated. txd 0 /p8 3 switch bit 0 : functions as txd 0. 1 : functions as p8 3. txd 1 /p8 7 switch bit 0 : functions as txd 1. 1 : functions as p8 7. 76543210 serial i/o pin control register address ac 16 at reset x0 16 receive receive is enabled when bit 2 (rei flag) of uarti transmit/receive control register 1 is set to 1. as shown in figure 75, the frequency divider circuit (1/16) at the receiving side begin to work when a start bit arrives and the data is received. ________ if rtsi output is selected by setting bit 2 of uarti transmit/receive ________ control register 0 to 1 , the rtsi output is h when the rei flag is ________ 0 . when the rei flag changes to 1 , the rtsi output goes l to inform the receiver that reception has become enabled. when the ________ receive operation starts, the rtsi output automatically becomes h . the entire transmission data bits are received when the start bit passes the final bit of the receive block shown in figure 66. at this point, the contents of the receive register is transferred to the receive buffer register and bit 3 (rli flag) of uarti transmit/receive control register 1 is set to 1. in other words, the rii flag indicates that the receive buffer register contains data when it is set to 1. at this time, when the low-order byte of the uartk receive buffer register is read ________ out, rtsi output goes back to l to indicate that the register is ready to receive the next data. bit 4 (oeri flag) of uarti transmit/receive control register 1 is set to 1 when the next data is transferred from the receive register to the receive buffer register while the rii flag is 1 , in other words, when an overrun error occurs. if the oeri flag is 1 , it indicates that the next data has been transferred to the receive buffer register before the contents of the receive buffer register has been read. bit 5 (feri flag) is set to 1 when the number of stop bits is less than required (framing error). bit 6 (peri flag) is set to 1 when a parity error occurs. bit 7 (sumi flag) is set to 1 when either the oeri flag, feri flag, or the peri flag is set to 1. therefore, the sumi flag can be used to determine whether there is an error. the setting of the rii flag, oeri flag, feri flag, and the peri flag is performed while transferring the contents of the receive register to the receive buffer register.
75 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers the feri, peri, and sumi flags are cleared to 0 when reading the low-order byte of the receive buffer register or when writing 0 to the rei flag. the oeri flag is cleared to 0 when writing 0 to the rei flag. interrupt request at completion of reception when the rik flag changes from 0 to 1 , in other words, when the receive operation is completed, the interrupt request bit of the uartk receive interrupt control register can be set to 1 . the timing when this interrupt request bit is to be set to 1 can be selected from the following: each reception when an error occurs at reception if bit 5 of the uartk transmit/receive control register 0 (uart re- ceive interrupt mode select bit) is cleared to 0 , the interrupt request bit is set to 1 at each reception. if bit 5 is set to 1 , the interrupt request bit is set to 1 only when an error occurs. (in the clock asyn- chronous serial communication, when an overrun error, framing er- ror, or parity error occurs, the interrupt request bit is set to 1 .) sleep mode the sleep mode is used to communicate only between certain micro- computers when multiple microcomputers are connected through serial i/o. the microcomputer enters the sleep mode when bit 7 of uarti transmit/receive mode register is set to 1. the operation of the sleep mode for an 8-bit asynchronous commu- nication is described below. when sleep mode is selected, the contents of the receive register is not transferred to the receive buffer register if bit 7 (bit 6 if 7-bit asyn- chronous communication and bit 8 if 9-bit asynchronous communi- cation) of the received data is 0 . also the rii, oeri, feri, peri, and the sumi flags are unchanged. therefore, the interrupt request bit of the uarti receive interrupt control register is also unchanged. normal receive operation takes place when bit 7 of the received data is 1 . the following is an example of how the sleep mode can be used. the main microcomputer first sends data: bit 7 is 1 and bits 0 to 6 are set to the address of the subordinate microcomputer to be com- municated with. then all subordinate microcomputers receive this data. each subordinate microcomputer checks the received data, clears the sleep bit to 0 if bits 0 to 6 are its own address and sets the sleep bit to 1 if not. next, the main microcomputer sends data with bit 7 cleared. then the microcomputer which cleared the sleep bit will receive the data, but the microcomputers which set the sleep bit to 1 will not. in this way, the main microcomputer is able to com- municate only with the designated microcomputer. precautions for clock asynchronous (uart) serial communication ________ ________ when using pin cts 0 /rts 0 , be sure to clear the d-a 2 output enable _______ bit (bit 2 at address 96 16 ) to 0 (output disabled). also, when ctsi _______ and rtsi are separated, pin clki cannot be used. therefore, when _______ _______ ctsi and rtsi are separated in uart mode, be sure to select an internal clock. before transmit operation is performed, be sure to clear bits 2 and 3 of the serial i/o pin control register (address ac 16 ) to 00 .
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 76 a-d converter the a-d converter is a 10-bit successive approximation converter. figure 77 shows the block diagram of the a-d converter, figure 78 shows the bit configuration of the a-d control register 0 (address 1e 16 ), and figure 79 shows the bit configuration of the a-d control register 1 (address 1f 16 ). a-d conversion accuracy bit 3 of a-d control register 1 is used to select whether to regard the conversion result as 10-bit or as 8-bit data. the conversion result is regarded as 10-bit data when bit 3 is ??and as 8-bit data when bit 3 is ?? when the conversion result is used as 10-bit data, the low-order 8 bits of the conversion result is stored in the even address of the cor- responding a-d register and the high-order 2 bits are stored in bits 0 and 1 at the odd address of the corresponding a-d register. bits 2 to 7 of the a-d register odd address are ?00000 2 ?when read. fig. 77 block diagram of a-d converter when the conversion result is used as 8-bit data, the conversion re- sult are stored in even address of the corresponding a-d register. in this case, the value at the a-d registers odd address is ?0 16 ?when read. a-d conversion frequency an operation clock ( ad ) of an a-d converter can be selected with bit 7 of the a-d control register 0 and bit 4 of the a-d control register 1. when bit 4 of the a-d control register 1 is ?? ad becomes f 2 /4 when bit 7 of the a-d control register 0 is ?? ad becomes f 2 /2 when bit 7 of the a-d control register 0 is ?? when bit 4 of the a-d control register 1 is ?? ad becomes f 2 when bit 7 of the a-d control register 0 is ?? ad becomes f 1 when bit 7 of the a-d control register 0 is ?? note that ad = f 1 (in other words, the fastest speed) can be selected only in the 8-bit mode. ad during a-d conversion must be 250 khz or more because the comparator uses a capacity coupling amplifier. comparator resistor ladder network selector an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 /ad trg v ref successive approximation register a-d register 0 a-d register 1 a-d register 2 a-d register 3 data bus (odd) a-d control register 1 a-d control register 0 ad a-d conversion frequency ( ad ) select bit 1,0 (1,1) a-d conversion frequency selection f 2 (1,0) (0,1) (0,0) 1/2 1/2 f 1 data bus (even) av ss v ref 0 1 v ref connection select bit a-d register 4 a-d register 5 a-d register 6 a-d register 7 decoder
77 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers trigger a-d conversion can be started by an internal trigger or by an exter- nal trigger. an internal trigger is selected when bit 5 of a-d control register 0 is 0 and an external trigger is selected when it is 1 . when trigger is selected, a-d conversion is started when bit 6 (a-d conversion start bit) is set to 1. when an external trigger is selected, the polarity of a trigger input can be selected by bit 5 of the a-d control register 1. when bit 5 = 0 , a falling edge is selected, and when bit 5 = 1 , a rising edge is selected. a-d conversion starts when the a-d conversion start bit is 1 and the ______ ad trg input changes from h to l (or l to h. ) in this case, the pins that can be used for a-d conversion are an 0 to an 6 because the ______ ad trg pin is multiplexed with an analog voltage input pin, an 7 . if an fig. 78 bit configuration of a-d control register 0 external trigger is selected, even when the a-d conversion is com- pleted, the a-d conversion start bit keeps 1 . also, a retrigger can be available even when a-d conversion is in progress. v ref connection whether to connect the reference voltage input (v ref ) with the resis- tor ladder network or not depends on bit 6 of the a-d control register 1. the v ref pin is connected when bit 6 is 0 and is disconnected when bit 6 is 1 (high impedance state). when a-d conversion is not performed, current from the v ref pin to the resistor ladder network can be cut off by disconnecting resistor ladder network from the v ref pin. before starting a-d conversion, wait for 1 s or more after clearing bit 6 to 0 . a-d control register 0 notes 1: ignored in the single sweep and repeat sweep modes. (each of these bits may be 0 or 1 .) 2: when using the an 4 pin, be sure to clear the int 3 pin select bit (bit 5 at address 94 16 ) to 0 . 3: when using the an 5 pin, be sure to clear the int 4 pin select bit (bit 6 at address 94 16 ) to 0 . 4: when using the an 6 pin, be sure to clear the d-a 0 output enable bit (bit 0 at address 96 16 ) to 0 (output disabled). 5: when using the an 7 pin, be sure to clear both of the int 2 pin select bit (bit 4 at address 94 16 ) and the d-a 1 output enable bit (bit 1 at address 96 16 ) to 0 . 6: when using an external trigger, be sure to clear the int 2 pin select bit (bit 4 at address 94 16 ) and d-a 1 output enable bit (bit 1 at address 96 16 ) to 0 . 7: for writing to this bit, use the movm (movmb) instruction, or the sta (stab, stad) instruction. 8: rewriting to each bit of the a-d control register 0 (except for bit 6) must be performed while a-d conversion is stopped. address 1e 16 76543210 analog input select bits (note 1) (valid in the one-shot and repeat modes.) 0 0 0 : select an 0 0 0 1 : select an 1 0 1 0 : select an 2 0 1 1 : select an 3 1 0 0 : select an 4 (note 2) 1 0 1 : select an 5 (note 3) 1 1 0 : select an 6 (note 4) 1 1 1 : select an 7 (note 5) a-d operation mode select bits 0 0 : one-shot mode 0 1 : repeat mode 1 0 : single sweep mode 1 1 : repeat sweep mode trigger select bit 0 : internal trigger 1 : external trigger due to ad trg input (note 6) a-d conversion start bit (note 7) 0 : stop a-d conversion 1 : start a-d conversion a-d conversion frequency ( ad ) select bit 0
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 78 fig. 79 bit configuration of a-d control register 1 0 76543210 a-d sweep pin select bits (note 1) (valid in the single sweep mode and repeat sweep mode.) 0 0 : an 0 , an 1 0 1 : an 0 an 3 1 0 : an 0 an 5 1 1 : an 0 an 7 must be 0 . resolution select bit 0: 8-bit mode 1: 10-bit mode a-d conversion frequency ( ad ) select bit 1 external trigger polarity select bit (valid when external trigger is selected.) 0: falling edge of input signal to the ad trg pin 1: rising edge of input signal to the ad trg pin v ref connection select bit (note 6) 0 : v ref is connected. 1 : v ref is not connected. 0 at read. (2 pins) (4 pins) (6 pins) (notes 2, 3) (8 pins) (notes 2 to 5) a-d control register 1 address 1f 16 a-d conversion frequency ( ad ) select bit bit 1 0 0 1 0 0 1 bit 0 ad f 2 /4 f 2 /2 f 2 1 1 f 1 (selectable only in 8-bit mode) notes 1: ignored in the one-shot and repeat modes. (each of these bits may be 0 or 1 .) 2: when using the an 4 pin, be sure to clear the int 3 pin select bit (bit 5 at address 94 16 ) to 0 . 3: when using the an 5 pin, be sure to clear the int 4 pin select bit (bit 6 at address 94 16 ) to 0 . 4: when using the an 6 pin, be sure to clear the d-a 0 output enable bit (bit 0 at address 96 16 ) to 0 (output disabled). 5: when using the an 7 pin, be sure to clear both of the int 2 pin select bit (bit 4 at address 94 16 ) and the d-a 1 output enable bit (bit 1 at address 96 16 ) to 0 . when an external trigger is selected, the an 7 pin cannot be used as an analog input pin. 6: once this bit is cleared from 1 to 0 , it is necessary to wait for 1 s or more before the a-d or d-a conversion starts. 7: rewriting to each bit of the a-d control register 1 must be performed while a-d conversion is stopped.
79 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers operation mode the operation mode is selected by bits 3 and 4 of a-d control regis- ter 0. the available operation modes are one-shot, repeat, single sweep, and repeat sweep. analog input port pins are multiplexed with port p7 pins. therefore, bits which correspond to pins for a-d conversion must be 0 (input mode). (1) one-shot mode one-shot mode is selected when bits 3 and 4 of a-d control register 0 are 0 is 0 . the a-d conversion pins are selected with bits 0 to 2 of a-d control register 0. a-d conversion can be started by a soft- ware trigger or by an external trigger. when an internal trigger is selected, a-d conversion is started when bit 6 (a-d conversion start bit) is set to 1. when bit 3 of the a-d control register 1 is 1 , a-d conversion ends after 59 ad cycles, and the interrupt request bit of the a-d interrupt control register is set to 1. at the same time, a-d control register 0 bit 6 (a-d conversion start bit) is cleared to 0 and a-d conversion stops. the result of a-d conversion is stored in the a-d register cor- responding to the selected pin. if an external trigger is selected, a-d conversion starts when the a-d conversion start bit is 1 and a valid edge is input to the ad trg pin, this operation is the same as that for internal trigger except that the a-d conversion start bit is not cleared after a-d conversion and a retrigger can be available during a-d conversion. (2) repeat mode repeat mode is selected when bit 3 of a-d control register 0 is 1 and bit 4 is 0 . the operation of this mode is the same as the operation of one-shot mode except that when a-d conversion of the selected pin is com- plete and the result is stored in the a-d register, conversion does not stop, but is repeated. no interrupt request is generated in this mode. furthermore, if an external trigger is selected, the a-d conversion start bit is not cleared. the contents of the a-d register can be read at any time. (3) single sweep mode single sweep mode is selected when bit 3 of a-d control register 0 is 0 and bit 4 is 1 . in the single sweep mode, the number of analog input pins to be swept can be selected. analog input pins are selected by bits 1 and 0 of the a-d control register 1 (address 1f 16 ). two pins, four pins, six pins, or eight pins can be selected as analog input pins, depending on the contents of these bits. a-d conversion is performed only for selected input pins. after a-d conversion is performed for input of an 0 pin, the conversion result is stored in a-d register 0, and in the same way, a-d conversion is per- formed for selected pins one after another. after a-d conversion is performed for all selected pins, the sweep is stopped. a-d conversion can be started with an internal trigger or with an ex- ternal trigger input. an internal trigger is selected when bit 5 of the a- d control register 0 (address 1e 16 ) is 0 and an external trigger is selected when it is 1 . when an internal trigger is selected, a-d conversion is started when a-d control register 0 bit 6. (a-d conversion start bit) is set to 1. when a-d conversion of all selected pins end, the interrupt request bit of the a-d conversion interrupt control register is set to 1. at the same time, a-d conversion start bit is cleared to 0 and a-d conver- sion stops. when an external trigger is selected, a-d conversion starts when the a-d conversion start bit is 1 and a valid edge is input to the ad trg pin. in this case, the a-d conversion result which is stored in the a-d register 7 becomes invalid. the operation by external trigger is the same as that by an internal trigger except that the a-d conversion start bit is not cleared to 0 after a-d conversion and a retrigger can be available during a-d conversion. (4) repeat sweep mode repeat sweep mode is selected when bit 3 of a-d control register 0 is 1 and bit 4 is 1 . the difference from the single sweep mode is that a-d conversion does not stop after conversion for all selected pins, but repeats again from the an 0 pin. the repeat is performed among the selected pins. also, no interrupt request is generated. furthermore, if an internal trigger is selected, the a-d convension start bit is not cleared. the a-d register can be read at any time. precautions for a-d conversion interrupt function clear the interrupt request bit of the a-d interrupt control register (bit 3 at address 70 16 ) before using the a-d interrupt. it is because the interrupt request bit is undefined just after reset.
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 80 d-a converter three independent d-a converters are included in this microcom- puter, and each d-a converter adopts an 8-bit r-2r method. figure 80 shows the block diagram of the d-a converter, figure 81 shows the bit configuration of the a-d control register 1, and figure 82 shows the bit configuration of the d-a control register. d-a conversion is performed by writing a value to the corresponding d-a register i. whether to output the analog voltage or not is deter- mined by bits 0 to 2 of the d-a control register. when any of bits 0 to 2 = ?? the corresponding pin (d-a 0 to d-a 2 ) outputs the analog volt- age. this analog voltage (v) is determined according to value n. (??= decimal number. this has been set in the d-a register.) v = v ref ? n/256 (n = 0 to 255) v ref : reference voltage the contents of the corresponding d-a output enable bit and d-a register are cleared to ??at reset. whether to connect the reference voltage input (v ref ) with the ladder network or not depends on bit 6 of the a-d control register 1. pin v ref is connected with the ladder network when bit 6 = ??and is disconnected when bit 6 = ??(high impedance state). when not performing the a-d or d-a conversion, current from pin v ref to the ladder network can be cut off by discon- necting ladder network from pin v ref . before starting a-d or d-a conversion, be sure to clear bit 6 to ?? and then, insert a waiting time of 1 ? or more. an external buffer is necessary when connecting a low impedance load with the d-a converter. it is because that a d-a output pin doesn? include a buffer. pin d-ai is multiplexed with i/o port pins, analog input pins, serial i/o pins, and external interrupt input pins. when a d-a i output enable bit = ??(in other words, output is enabled.), however, the corre- sponding pin cannot function as another i/o pin, which is multiplexed fig. 80 block diagram of d-a converter fig. 81 bit configuration of a-d control register 1 note: when bit 6 has been cleared to 0 from 1 , insert a waiting time of 1 ??? ?? (note) 0: connected. 1: disconnected. a-d control register 1 address 1f 16 ? ? (note) 0: output is disabled. 1: output is enabled. d-a 1 output enable bit (note) 0: output is disabled. 1: output is enabled. d-a 2 output enable bit (note) 0: output is disabled. 1: output is enabled. 76543210 d-a control register address 96 16 note: pin d-ai is multiplexed with i/o port pins, analog input pins, serial i/o pins, and external interrupt input pins. when a d-ai output enable bit = 1 (in other words, output is enabled.), however, the corresponding pin cannot function as another i/o pin, which is multiplexed with pin d-ai. with pin d-ai. also, when not using the d-a converter, be sure to clear the contents of the corresponding d-a output enable bit and d-a register to 0 .
81 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers real-time output the real-time output function enables to change the output level of several pins simultaneously with a specified timer s counting. whether to use the real-time output function is decided by the wave- form output select bits of the 8-bit real-time output control register (bits 0 and 1 at address a0 16 ). (see figure 83.) also, the real-time output controlled by the pulse output mode select bit of the real-time output control register (bit 2 at address a0 16 ) and is used in one of the following ways: 4 bits ? 6 bits ? ? (1) pulse mode 0 when the pulse output mode select bit is cleared to 0 , the micro- computer enters pulse output port is controlled by 2 groups of 4 bits. figures 84 and 85 show the bit configuration of the pulse output data register 0/1 (address a2 16 /a4 16 ) and real-time output structure in pulse mode 0, respectively. when the waveform output select bits are set to 01 (bit 1 = 0 and bit 0 = 1 ), rtp0 3 to rtp0 0 become pulse output port pins, in other words, rtp0 is selected. when the waveform output select bits are set to 10 (bit 1 = 1 and bit 0 = 0 ), rtp1 3 to rtp1 0 become pulse output port pins, in other words, rtp1 is selected. when the waveform output select bits are set to 11 (bit 1 = 1 and bit 0 = 1 ), two groups consisting of rtp1 3 to rtp1 0 and rtp0 3 to rtp0 0 become pulse output port pins, in other words, rtp1 and rtp0 are selected. when the waveform output select bits are set to 00 (bit 1 = bit 0 = 0 ), port p5 pins become normal programmable i/o port pins. the contents of the pulse output data register 1 (high-order 4 bits at address a4 16 ), which corresponds to rtp1 3 to rtp1 0 , is output to these ports each time when the contents of timer a1 counter be- comes 0000 16 . the contents of the pulse output data register 0 fig. 83 bit configuration real-time output control register fig. 84 bit configuration of pulse output data register real-time output register a0 16 waveform output select bits 00 : programmable i/o port 01 : rtp0 selected when pulse mode 0 is selected: rtp0 when pulse mode 1 is selected: rtp0 1 , rtp0 0 10 : rtp1 selected when pulse mode 0 is selected: rtp1 when pulse mode 1 is selected: rtp1, rtp0 3 , rtp0 2 11 : rtp1 and rtp0 selected when pulse mode 0 is selected: rtp1 and rtp0 when pulse mode 1 is selected: rtp1, rtp0 3, rtp0 2 and rtp0 1, rtp0 0 pulse output mode select bit 0 : pulse mode 0 1 : pulse mode 1 0 at read. 76543210 address note 1: used only in pulse mode 0 2: used only in pulse mode 1 pulse output data register 0 rtp0 0 pulse output data bit rtp0 1 pulse output data bit rtp0 2 pulse output data bit (note 1) rtp0 3 pulse output data bit (note 1) 76543210 address a2 16 pulse output data register 1 rtp0 2 pulse output data bit (note 2) rtp0 3 pulse output data bit (note 2) rtp1 0 pulse output data bit rtp1 1 pulse output data bit rtp1 2 pulse output data bit rtp1 3 pulse output data bit 76543210 address a4 16 (low-order 4 bits at address a2 16 ), which corresponds to rtp0 3 to rtp0 0 , is output to these ports each time when the contents of timer a0 counter becomes 0000 16 . when 0 is written to a specified bit of the pulse output data register, a low-level signal is output to a pulse output port if the counter con- tents of the timer which corresponds to the bit becomes 0000 16 : when 1 is written to the bit, a high-level signal is output to a pulse output port which corresponds to the bit at the same timing.
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 82 fig. 85 real-time output structure in pulse mode 0 (2) pulse mode 1 when the pulse output mode select bit is set to 1 , the microcom- puter enters pulse mode 1, and a pulse output port pins are sepa- rately controlled (6 bits and 2 bits). figures 86 shows the real-time output structure in pulse mode 1. when the waveform output select bits are set to 01 (bit 1 = 0 and bit 0 = 1 ), rtp1 3 to rtp1 0 , rtp0 3 , and rtp0 2 become program- mable i/o port pins. simultaneously, rtp0 1 and rtp0 0 become pulse output port pins. when the waveform output select bits are set to 10 (bit 1 = 1 and bit 0 = 0 ), rtp1 3 to rtp1 0 , rtp0 3 , and rtp0 2 become pulse out- put port pins. at this time, rtp0 1 and rtp0 0 become programmable i/o port pins. when the waveform output select bits are set to 11 (bit 1 = bit 0 = t dq dq dq dq t dq dq dq d 6 d 5 d 4 d 3 d 2 d 1 d 0 timer a0 timer a2 p5 3 /rtp0 3 p5 2 /rtp0 2 p5 1 /rtp0 1 p5 0 /rtp0 0 port p5 i latch waveform output select bit (address a0 16 ) bit 1 pulse output data register 0 (address a2 16 ) pulse output data register 1 (address a4 16 ) data bus (even) pulse output mode select bit (address a0 16 ) 0 d 7 t t t dq t t t a a a a a a a a waveform output select bit (address a0 16 ) bit 0 p5 7 /rtp1 3 p5 6 /rtp1 2 p5 5 /rtp1 1 p5 4 /rtp1 0 port p5 i direction register 1 0 (i = 7 to 0) a (address d 16 ) (address b 16 ) 1 ), pulse output port pins are divided into two groups; one consists of rtp1 3 to rtp1 0 , rtp0 3 , rtp0 2 and the other consists of rtp0 1 and rtp0 0 . when the waveform output select bits are set to 00 (bit 1 = bit 0 = 0 ), port p5 pins become normal programmable i/o port pins. rtp1 3 to rtp1 0 , rtp0 3 , and rtp0 2 are controlled by timer a2. also, rtp0 1 and rtp0 0 are controlled by timer a0. the contents of the pulse output data register 1 (high-order 6 bits at address a4 16 ), which corresponds to rtp1 3 to rtp1 0 , rtp0 3 , and rtp0 2 , are output to this port each time when the contents of timer a2 counter becomes 0000 16 . the contents of the pulse output data register 0 (low-order 2 bits at address a2 16 ), which corresponds to rtp0 1 and rtp0 0 , are output to this port each time when the con- tents of timer a0 counter become 0000 16 .
83 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers fig. 86 real-time output structure in pulse mode 1 table 14 lists the port p5/rtp pin output when all of the port p5 di- rection registers are set to the output mode. precautions for real-time output function after reset, the port p5 direction register is set to the input mode, and port p5i (i = 0 to 7) pins function as normal i/o port pins. when using these pins as real-time output port pins, set the corresponding bits of the port p5 direction register to the output mode. additionally, by reading the real-time output port s value from the port p5 register, output level of pins can be read out. real-time output control register (address a0 16 ) store address for port p5/rtp pin output data 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 1 0b 0b a4 a4 0b 0b a4 a4 0b 0b a4 a4 0b 0b a4 a4 0b 0b a4 a4 0b 0b a4 a4 0b 0b a4 a4 0b 0b a4 a4 0b a2 0b a2 0b 0b a4 a4 0b a2 0b a2 0b 0b a4 a4 0b a2 0b a2 0b a2 0b a2 0b a2 0b a2 0b a2 0b a2 table 14 port p5/rtp pin output dq dq dq dq t dq dq dq d 6 d 5 d 4 d 3 d 2 d 1 d 0 timer a0 timer a2 p5 3 /rtp0 3 p5 2 /rtp0 2 p5 1 /rtp0 1 p5 0 /rtp0 0 port p5 i latch waveform output select bit (address a0 16 ) bit 1 pulse output data register 0 (address a2 16 ) pulse output data register 1 (address a4 16 ) data bus (even) pulse output mode select bit (address a0 16 ) 1 d 7 t t t dq t t a a a a a a a a waveform output select bit (address a0 16 ) bit 0 p5 7 /rtp1 3 p5 6 /rtp1 2 p5 5 /rtp1 1 p5 4 /rtp1 0 port p5 i direction register 1 0 (i = 7 to 0) a t t (address d 16 ) (address b 16 ) address 0b 16 : port p5 address a2 16 : pulse output data register 0 address a4 16 : pulse output data register 1
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 84 1/16 watchdog timer frequency select bit fff 16 is set. writing to watchdog timer register stp instruction watchdog timer interrupt request wf 32 wf 512 watchdog timer f 2 wait mode access to external area hlda 1/16 1 0 watchdog timer register: address 60 16 watchdog timer frequency select register: bit 0 at address 61 16 watchdog timer clock source select bits at stp state termination: bits 6, 7 at address 61 16 ? 0 , this signal will be generated. note: during the stop mode and until the stop mode is terminated, setting for disabling the watchdog timer is ignored. reset ? (note) . fx 16 fx 32 fx 64 fx 128 watchdog timer clock source select bits at stp state termination stop mode divided f(x in ) watchdog timer the watchdog timer is used to detect unexpected execution se- quence caused by software runaway and others. figure 87 shows the block diagram of the watchdog timer. the watchdog timer consists of a 12-bit binary counter. the watchdog timer counts clock wf 32 , which is obtained by dividing the peripheral devices clock f 2 by 16; or clock wf 512 , which is ob- tained by doing it by 256. bit 0 of the watchdog timer frequency se- lect register (watchdog timer frequency select bit) shown in figure 88 selects which clock is to be counted. wf 512 is selected when this bit 0 is 0 , and wf 32 is selected when bit 0 is 1 . bit 0 is cleared to 0 after reset. fff 16 is set in the watchdog timer when l level voltage is applied to pin reset, stp instruction is executed, data is written to the watchdog timer register (address 60 16 ), or the most significant bit of the watchdog timer becomes 0 . after fff 16 is set in the watchdog timer, when the watchdog timer counts wf 32 or wf 512 by 2048 counts, the most significant bit of watchdog timer becomes 0 , the watchdog timer interrupt request bit is set to 1 , and fff 16 is set again in the watchdog timer. in program coding, make sure that data is written in the watchdog timer before the most significant bit of the watchdog timer becomes 0 . if this routine is not executed owing to unexpected program ex- ecution or others, the most significant bit of the watchdog timer be- fig. 87 block diagram of watchdog timer fig. 88 bit configuration of watchdog timer frequency select register 76543210 watchdog timer frequency select register watchdog timer frequency select bit 0 : w f 512 1 : w f 32 watchdog timer clock source select bits at stp state termination 0 0 : fx 32 0 1 : fx 16 1 0 : fx 128 1 1 : fx 64 76543210 address 61 16 comes 0 and an interrupt is generated. the microcomputer can generate a reset pulse by writing 1 to bit 6 (software reset bit) of processor mode register 0 in an interrupt rou- tine and can be restarted. the watchdog timer can also be used to return from the stp state, where a clock has stopped its operation owing to the stp instruction execution. for details, refer to the sections on the clock generating circuit and standby function. the watchdog timer stops its operation in the following cases, and at this time, input to the watchdog timer is disabled: when the external area is accessed in the hold state in the wait mode in the stop mode
85 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers how to disable watchdog timer when not using the watchdog timer, it can be disabled. when the watchdog timer is disabled, it s operation stops and no watchdog timer interrupt has been generated. setting for disabling the watchdog timer is possible by writing 79 16 and 50 16 to the particular function select register 2 (address 64 16 ) sequentially with the following instructions: movmb/stab instruction, or movm/sta instruction (m = 1) if any method other than above has been adopted in order to access (in other words, read/write) the particular function select register 2, the watchdog timer will not be disabled until reset operation is per- formed. (also, reset is the only one method to remove the setting for disabling the watchdog timer.) moreover, this setting for disabling the watchdog timer is ignored at return from the stp mode, and the watchdog timer operates. (for details, refer to the section on the standby function.)
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 86 input/output pins ports p0 to p8, p10, p11 all have the direction register, and each bit can be programmed for input or output. a pin becomes an output pin when the corresponding bit of direction register is 1 , and an input pin when it is 0 . when a pin is programmed for output, the data is written to its port latch and it is output to the output pin. when a pin is programmed for output, the contents of the port latch is read instead of the value of the pin. accordingly, a previously output value can be read correctly even when the output h voltage is lowered or the output l voltage is raised owing to an external load, etc. a pin programmed as an input pin is in the flooting state, and the value input to the pin can be read. when a pin is programmed as an input pin, the data is written only in the port latch and the pin remains floating. each of figures 89 and 90 shows the block diagram for each port pin and pin nmi. figure 91 shows the bit configuration of the port func- tion control register. bit 3 of the port function control register serves as the port p0 input level select bit, which selects the v ih /v il level under the condition that port p0 is used as an input port. bit 4 of the port function control register serves as the p4 4 p4 7 pullup connection select bit. this bit determines whether port pins p4 4 p4 7 , which are multiplexed with chip select pins, are to be pulled up or not. at reset, this bit 4 = 0 and p 4 p4 7 are pulled up. the pullup function is valid only when the corresponding port is used an input port. bit 7 of the port function control register serves as the nmi pullup connection select bit. at reset, this bit 7 = 0 and pin nmi is pulled up. the pullup function is valid only when the corresponding port is used as an input port. when using port pins p5 4 p5 7 as the key input interrupt input pins (ki 0 to ki 3 ), the pullup function can be selected, also. for details, refer to the section on interrupts. when using a port pin as an internal peripheral device s input pin, clear the corresponding port direction register s bit to 0 . when us- ing a port pin as an internal peripheral device s output pin, the port direction register s bit may be 0 or 1 . in the memory expansion or microprocessor mode, port pins of p0 to p4, p10, p11 become i/o pins, and the their functions as i/o port pins are invalid. note that, however, some port pins can function as port pins by the special setting. for details, refer to the section on the processor modes. fig. 91 bit configuration of port function control register notes 1: for the m37902fxm (power source voltage = 3.3 v 2: when md1 = v cc and md0 = v cc (flash memory parallel i/o mode), pins p4 4 to p4 7 and nmi are not pulled up, regardless of these bits contents. 3: when md1 = v ss and md0 = v cc (microprocessor mode), pin cs 0 (p4 4 ) is not pulled up, regardless of the bit s contents. 76543210 port function control register port p0 input level select bit 0 : v ih = 0.7v cc , v il = 0.2v cc 1 : v ih = 0.43v cc (note 1) , v il = 0.16v cc address/port switch bits 000 : a 0 to a 23 (16 mbytes) 001 : a 0 to a 21 , p0 6 , p0 7 (4 mbytes) 010 : a 0 to a 19 , p0 4 to p0 7 (1 mbytes) 011 : a 0 to a 17 , p0 2 to p0 7 (256 kbytes) 100 : a 0 to a 15 , p0 0 to p0 7 (64 kbytes) 101 : do not select. 110 : a 0 to a 11 , p0 0 to p0 7 , p11 4 to p11 7 (4 kbytes) 111 : a 0 to a 7 , p0 0 to p0 7 , p11 0 to p11 7 (256 bytes) pins p4 4 p4 7 pullup connection select bit (notes 2 and 3) 0 : pins p4 4 p4 7 are pulled up. 1 : pins p4 4 p4 7 are not pulled up. address 92 16 pin nmi pullup connection select bit (note 2) 0 : pin nmi is pulled up. 1 : pin nmi is not pulled up. fix these bits to 0 . 0 0 at reset 00 16
87 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers fig. 89 block diagram for each port pin and pin nmi (1) [inside dotted-line not included] p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 1 to p3 3 , p10 0 to p10 7 , p11 0 to p11 7 [inside dotted-line included] p3 0 /rdy, p4 3 /hold, p6 1 /ta4 in , p6 2 /int 0 , p6 3 /int 1 , p6 4 /int 2 , p6 5 /tb0 in , p6 6 /tb1 in , p6 7 /tb2 in , p8 2 /r x d 0 , p8 6 /r x d 1 [shaded area not included] p5 1 /ta0 in /rtp0 1 , p5 3 /ta1 in /rtp0 3 [shaded area included] p5 5 /ta2 in /rtp1 1 /ki 1 , p5 7 /ta3 in /rtp1 3 /ki 3 [inside dotted-line not included] p4 0 /ale, p4 1 /
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 88 p8 1 /cts 0 /clk 0 , p8 4 /cts 1 /rts 1 /int 4 , p8 5 /cts 1 /clk 1 [inside dotted-line not included] p7 0 /an 0 , p7 1 /an 1 , p7 2 /an 2 , p7 3 /an 3 [inside dotted-line included] p7 4 /an 4 /(int 3 ), p7 5 /an 5 /(int 4 ) p8 0 /cts 0 /rts 0 /da 2 /int 3 [inside dotted-line not included] p7 6 /an 6 /da 0 [inside dotted-line included] p7 7 /an 7 /ad trg /da 1 /(int 2 ) analog input analog output enable d-a output 1 0 1 0 analog output enable d-a output analog input nmi pullup selection data bus port latch direction register data bus port latch direction register data bus port latch direction register data bus port latch direction register pullup transistor output (internal peripheral devices) output (internal peripheral devices) fig. 90 block diagram for each port pin and pin nmi (2)
89 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers fig. 93 microcomputer internal register s status at reset (2) ( 80 16 ) address cs 0 control register l ( 81 16 ) cs 0 control register h ( 82 16 ) cs 1 control register l ( 83 16 ) cs 1 control register h ( 8c 16 ) area cs 1 start address register ( 84 16 ) cs 2 control register l ( 85 16 ) cs 2 control register h ( 86 16 ) cs 3 control register l ( 87 16 ) cs 3 control register h ( 8a 16 ) area cs 0 start address register ( 8e 16 ) area cs 2 start address register ( 90 16 ) area cs 3 start address register notes 1: the contents of the other registers and ram are undefined at reset and must be initialized by software. 2: while vss level voltage is applied to pin md0, this bit is 0 . while vcc level voltage is applied to pin md0, on the other hand, this bit is 1 . 3: while vss level voltage is applied to pin byte, these bits are 0 . while vcc level voltage is applied to pin byte, on the other hand, these bits are 1 . ( 92 16 ) port function control register ( 94 16 ) external interrupt input control register ( 96 16 ) d-a control register address 0 10 (note 3) 10 0 10 010 0 10 010 0 10 010 0 001 0 000 0 000 0 000 0 000 0 000 0 000 0 000 000 0 1 001 0 0 0 000 0 0 0 000 0000 0000 000 00 16 00 16 program bank register pg contents at address ffff 16 program counter pc h contents at address fffe 16 program counter pc l 0000 16 direct page registers dpr0 to dpr3 data bank register dt fff 16 stack pointer ( 98 16 ) d-a register 0 ( 99 16 ) d-a register 1 ( 9a 16 ) d-a register 2 ( a0 16 ) real-time output control register ( ac 16 ) serial i/o pin control register ( bc 16 ) clock control register 000 0000 0 000 0 111 ( 9e 16 ) flash memory control register 0 00 001 0 000 0 000 0 00 16 00 16 00 16 processor status register ps 1?? 0 00 ?? 0 00 (note 3) (note 3) (note 3) (note 2) reset circuit while the power source voltage satisfies the recommended operat- ing condition, reset state is removed if pin reset s level returns from the stabilized l level to the h level. as a result, program ex- ecution starts from the reset vector address. this reset vector ad- dress is expressed as shown below: a 23 to a 16 = 00 16 a 15 to a 8 = contents at address ffff 16 a 7 to a 0 = contents at address fffe 16 figures 92 and 93 show the microcomputer internal register s status at reset, and figure 94 shows an operation example of the reset cir- cuit. apply l level voltage to pin reset for a period (2 ? or more) under the following conditions: pin vcc s level satisfies the recommended operating condition. oscillator s operation has been stabilized. fig. 94 operation example of reset circuit (note that proper evalua- tion is necessary in the system development stage.) v cc reset power on v cc level 0.2v cc level oscillation stabilized 2
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 90 fig. 92 microcomputer internal register s status at reset (1) 00 00 00 00 0 0 0 ( 04 16 ) address 00 16 ( 05 16 ) ( 08 16 ) ( 09 16 ) 00 16 ( 0c 16 ) ( 0d 16 ) 00 16 ( 10 16 ) ( 11 16 ) ( 14 16 ) ( 56 16 ) 00 16 ( 57 16 ) 00 16 ( 58 16 ) 00 16 ( 59 16 ) 00 16 ( 5a 16 ) 00 16 ( 18 16 ) 00 16 ( 19 16 ) 00 16 notes 1: the contents of the other registers and ram are undefined at reset and must be initialized by software. 2: while vss level voltage is applied to pin md0, these bits are 0 . while vcc level voltage is applied to pin md0, on the other hand, these bits are 1 . 3: at power-on reset, these bits are clear to 0 . at hardware or software reset, on the other hand, these bits retain the value just before reset. 0 000 0 ??? ( 1e 16 ) 0 000 011 ( 1f 16 ) 1 0 0 000 ( 34 16 ) 1 0 0 000 ( 3c 16 ) 0 000 0 010 ( 35 16 ) 0 000 0 010 ( 3d 16 ) 0 0 000 ( 42 16 ) 00 ( 45 16 ) ( 30 16 ) 00 16 ( 38 16 ) 00 16 0 ( 44 16 ) ( 40 16 ) 00 16 0 0? 0 000 ( 5b 16 ) 1 000 (note 2) 0 (note 2) 0 ( 5e 16 ) ( 5f 16 ) ( 60 16 ) address (note 3) 0 1 0000 0000 0 fff 16 ( 61 16 ) ( 62 16 ) ( 63 16 ) ( 66 16 ) ( 67 16 ) ( 6e 16 ) ( 6f 16 ) 0000 ?000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ( 72 16 ) ( 73 16 ) ( 74 16 ) ( 77 16 ) ( 78 16 ) ( 79 16 ) ( 7a 16 ) 0 00 000 ( 7c 16 ) 000 ( 7e 16 ) ( 70 16 ) ( 71 16 ) ( 75 16 ) ( 76 16 ) 0 00 000 ( 7d 16 ) ( 7b 16 ) ( 7f 16 ) 0 00 00 16 00 00 (note 2) 0 000 (note 3) 0000 00 16 00 16 (note 3) (note 3) 0 0 0 0? 0 000 ( 5c 16 ) 0 0? 0 000 ( 5d 16 ) 00 16 00 16 00 16 port p0 direction register port p1 direction register port p2 direction register port p3 direction register port p4 direction register port p5 direction register port p6 direction register port p7 direction register port p8 direction register timer a0 mode register timer a1 mode register timer a2 mode register timer a3 mode register timer a4 mode register a-d control register 0 a-d control register 1 uart 0 transmit/receive control register 0 uart 1 transmit/receive control register 0 uart 0 transmit/receive control register 1 uart 1 transmit/receive control register 1 one-shot start register timer a clock frequency select register port p10 direction register port p10 direction register uart 0 transmit/receive mode register uart 1 transmit/receive mode register up-down register count start register timer b0 mode register timer b1 mode register timer b2 mode register processor mode register 0 processor mode register 1 watchdog timer watchdog timer frequency select register debug control register 1 debug control register 0 particular function select register 1 particular function select register 0 int 2 interrupt control register int 3 interrupt control register int 4 interrupt control register uart 0 receive interrupt control register uart 1 transmit interrupt control register uart 1 receive interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b0 interrupt control register timer b2 interrupt control register int 1 interrupt control register a-d conversion interrupt control register uart 0 transmit interrupt control register timer a0 interrupt control register timer a1 interrupt control register int 0 interrupt control register timer b1 interrupt control register
91 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers oscillation circuit an oscillation circuit locates between pins x in and x out , and figure 95 shows a circuit example with a oscillator (an external ceramic resonator or quartz crystal oscillator). the constants such as capaci- tance etc. depend on a oscillator. therefore, for these constants, adopt the oscillator manufacturer s recommended values. figure 96 shows a circuit example with an external clock source. when an external clock is input, be sure to leave pin x out open. also, in this case, when the external clock input select bit (bit 1 of the particular function select register 0; see figure 100.) is set to 1 , the oscillation circuit stops it s operation, and the current dissipation is reduced. moreover, this bit has another function, which selects the return condition from the stop mode. for details, refer to the section on the standby function. on the other hand, the pll (phase locked loop) frequency multi- plier (hereafter, referred as pll circuit.) is included, also. this pll circuit uses an clock input from pin x in and generates a multiplied clock. when using the pll circuit, be sure to connect pin v cont with an external filter circuit. (see figure 97.) when not using the pll cir- cuit, be sure to leave pin v cont open. when not using the pll circuit, be sure to clear the pll circuit op- eration enable bit (bit 1 of the clock control register; see figure 99.), so that the pll circuit will stop it s operation. fig. 95 circuit example with external ceramic resonator or quartz crystal oscillator fig. 96 circuit example with external clock source fig. 97 circuit example with pin v cont and pll circuit x in r f x out r d c in c out m37902 m37902 x in x out left open. external clock source vcc vss m37902 v cont 1 k ? note: make the wiring length as short as possible, and shield it with the gnd line which surrounds this circuit. also, for the clock supply to pin x in , see figures 95 and 96.
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 92 clock generating circuit figure 98 shows the block diagram of the clock generating circuit. the clock generating circuit consists of the clock oscillation circuit, pll frequency multiplier (pll circuit), system clock switch circuit, peripheral devices clock switch circuit, clock divider, standby control circuit, etc. as control registers for the clock generating circuit, also, the clock control register (address bc 16 ), particular function select register 0 (address 62 16 ) are provided. (see figures 99 and 100.) as shown in figure 98, clocks used in the cpu, biu, peripheral de- vices, watchdog timer (in other words, clocks cpu , biu , f 1 to f 4096 , wf 32 , wf 512 ) are made from system clock f sys . system clock f sys can be selected between fx in (in other words, a clock input from pin x in) and f pll (in other words, an output clock generated by the pll cir- cuit). by setting the clock 1 output select bit (bit 7 of the processor mode register 0) to ?? also, system clock f sys can be output from port pin p4 1 , as clock 1 . the pll circuits operation, system clock (f sys ) selection, and divide ratio selection for peripheral devices?clocks (f 1 to f 4096 ) are con- trolled by the clock control register. the following describes about these control. bit 1 of the clock control register (the pll circuit operation enable bit) selects the pll circuits operation (stopped/active). when this bit is set to ?? pin v cont will becomes valid, and the pll circuit will oper- ate. at reset, the pll circuit operation enable bit becomes ?? (in this case, the pll circuit operates.) when not using the pll circuit, be sure to clear the pll circuit operation enable bit to ??(stopped). at the stp instruction execution or while the flash memory parallel i/o mode is set, the pll circuit stops its operation, and pin v cont is in- valid, regardless of this bit 1s status. bits 2 and 3 of the clock control register (the pll multiplication ratio select bits) select the ratio of f pll /fx in . the pll multiplication ratio must be set so that the frequency of the pll output clock (f pll ) must be in the range from 10 mhz to 26 mhz. at reset, the pll multiplica- tion ratio select bits become ?,1?( ? 2). the change of the multipli- cation ratio must be performed while input clock fx in is set as system clock. (in this case, bit 5 of the clock control register = ??) after that, be sure to wait that the operation-stabilizing time of the pll circuit has passed, and switch the system clock to the pll output clock (f pll ). (in other words, set bit 5 to ??) note that, after reset, the pll multiplication ratio select bits are allowed to be changed only once. bit 5 of the clock control register is the system clock select bit, and fx in is selected as the system clock when bit 5 = ?? on the other hand, when bit 5 = ?? the pll output clock (f pll ) is selected. at re- set, the system clock select bit becomes ?? when selecting f pll , be sure that the pll circuits operation has been stabilized properly, and then, set the system clock select bit to ?? also, when the pll circuit operation enable bit is cleared to ??(the pll circuit is stopped.), the system clock select bit will automatically be cleared to ?? note that a value of ??cannot be written to the system clock select bit while the pll circuit operation enable bit =?? table 15 lists the f sys selection. bits 6 and 7 of the clock control register are the peripheral devices clock select bits 0, 1, and these bits select the multiplication ratio of (f 1 to f 4096 )/(f sys ). table 16 lists the internal peripheral devices operation clock fre- quency. at reset, these bits become ?, 0? table 15. f sys selection table 16. internal peripheral devices?operation clock frequency 10 ( ? 3) 01 ( ? 2) system clock f sys 11 ( ? 4) fx in f pll f pll f pll clock source frequency (note) note: the pll multiplication ratio must be set so that the frequency of the pll output clock (f pll ) must be in the range from 10 mhz to 26 mhz. f(x in ) means the frequency of the input clock from pin x in (fx in ). after reset, the pll multiplication ratio select bits are allowed to be changed only once. pll circuit operation enable bit (bit 1) system clock select bit (bit 5) 1 0 1 f(x in ) f(x in ) ? 2 f(x in ) ? 3 f(x in ) ? 4 pll multiplication ratio select bits (bits 3, 2) (note) f sys /16 f sys /2 peripheral devices clock select bits 1, 0 (bits 7, 6) f sys /64 f sys f sys f sys /8 f sys /32 1 0 1 1 note: when selecting the peripheral devices clock select bits 1, 0 = 01 2 , be sure that system clock f sys does not exceed 13 mhz. internal peripheral devices operation clock f 1 f 16 f sys /2 f sys /4 f sys /32 f sys /128 0 1 (note) 0 0 f 2 f 64 f 512 f 4096 f sys f sys /512 f sys /4096 f sys /256 f sys /2048 f sys /1024 f sys /8192 do not select.
93 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers fig. 98 block diagram of clock generating circuit f 2 f 64 f 512 f 4096 q r s stp instruction biu (clock for biu) cpu (clock for cpu) cpu wait request 1/4 1/8 1/8 reset watchdog timer frequency select bit : bit 0 at address 61 16 watchdog timer clock source select bit at stop state termination : bits 6, 7 at address 61 16 external clock input select bit : bit 1 at address 62 16 system clock stop select bit at wit : bit 3 at address 63 16 pll circuit operation enable bit : bit 1 at address bc 16 pll multiplication ratio select bits : bits 2, 3 at address bc 16 system clock select bit : bit 5 at address bc 16 peripheral device s clock select bit 0, 1 : bits 6, 7 at address bc 16 1/8 1/2 1/16 watchdog timer wf 32 wf 512 f 16 f 1 peripheral device s clocks 0 1 watchdog timer frequency select bit x in x out system clock stop select bi at wit 1/16 access to external area hlda 0 1 watchdog timer clock source select bit at stop state termination 1 wait mode 1 0 1 0 1/2 1 0 1 wait mode system clock frequency select bit pll frequency multiplier f pll v cont wait mode external clock input select bit q r s stp instruction interrupt request q r s wit instruction interrupt request wait mode pll circuit operation enable bit pll multiplication ratio select bits fx in f/n 0 fx 16 fx 32 fx 64 fx 128 fx 16 fx 32 fx 64 fx 128 peripheral device s clock select bit 0 peripheral device s clock select bit 1 biu : bus interface unit cpu : central processing unit ? : signal generated when the watchdog timer s most significant bit becomes 0 . f sys system clock frequency select bit ? operating clock for serial i/o, timer b a-d conversion frequency ( ad ) clock source operating clock for timer a external clock input select bit interrupt request
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 94 fig. 100 bit configuration of particular function select register 0 fig. 99 bit configuration of clock control register 76543210 clock control register fix this bit to 1 . pll circuit operation enable bit (note 1) 0: pll frequency multiplier is stopped, and pin v cont is invalid (floating state). 1: pll frequency multiplier is operating, and pin v cont is valid. pll multiplication ratio select bits (note 2) 00: do not select. 01: double 10: triple 11: quadruple fix this bit to 0 . system clock select bit (note 3) 0: fx in 1: f pll peripheral device s clock select bits 1, 0 see table 16. address bc 16 1 0 at reset 07 16 notes 1: when not using the pll frequency multiplier, clear this bit to 0 . in the stop mode or in the flash memory parallel i/o mode, the pll circuit stops it s operation regardless of this bit s contents; at this time, pin v cont is invalid. 2: when rewriting this bit, be sure to clear bit 5 to 0 simultaneously. also, after this bit is rewritten, insert a waiting time of 2 ms, and then set bit 5 to 1 . 3: when the pll circuit operation enable bit (bit 1) has been cleared to 0 , this bit will also be cleared to 0 . also, bit 1 = 0 , nothing can be written to this bit. (fixed to be 0 .) 76543210 particular function select register 0 external clock input select bit (note) 0: oscillation circuit is active. (oscillator is connected.) watchdog timer is used at stop mode termination. 1: oscillation circuit is inactive. (external clock is input.) when the system clock select bit = 0 , watchdog timer is not used at stop mode termination. when the system clock select bit = 1 , watchdog timer is used at stop mode termination. fix this bit to 0 . stp instruction invalidity select bit (note) 0: stp instruction is valid. 1: stp instruction is invalid. note: address 62 16 0 0 0 writing to these bits requires the following procedure: write 55 16 to this register. (the bit status does not change only by this writing.) succeedingly, write 0 or 1 to each bit. also, use the movm (movmb) instruction or sta (stab, stad) instruction
95 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers standby function the standby function provides the stop (hereafter called stp) and the wait (hereafter called wit) mode. these modes are used to save the power dissipation of the system, by stopping oscillation or sys- tem clock in the case that the cpu needs not be operating. the microcomputer enters the stp or wit mode by executing the stp or wit instruction, and either mode is terminated by acceptance of an interrupt request or reset. to terminate the stp or wit mode by an interrupt request, the inter- rupt to be used for termination of the stp or wit mode must be en- abled in advance to execution of the stp or wit instruction. the interrupt priority level of this interrupt is required to be higher than the processor interrupt priority level (ipl) of the routine where the stp or wit instruction will be executed. figures 100 to 102 show the bit configurations of the particular func- tion select registers 0, 1, and watchdog timer frequency select regis- ter respectively. setting the stp instruction invalidity select bit (bit 0 of the particular function select register 0) to 1 invalidates the stp instruction, and the stp instruction will be ignored. since the above bit is cleared to 0 after reset is removed, however, the stp instruc- tion is valid. the stp- or the wit-instruction-execution status bit (bit 0 or 1 of the particular function select register 1) is set to 1 by the execution of the stp or the wit instruction, and so, after the stp or wit mode has been terminated, each bit will indicate that the stp or wit in- struction has been executed. accordingly, each of these bits must be cleared to 0 by software at termination of the stp or the wit mode. table 17 explains the microcomputer s operation in the stp and wit modes. the external bus fixation function can also be provided. this function enables the user to specify the states of the external bus and the bus control signals in the memory expansion and the microprocessor mode in the stp or wit mode. for more information, refer to the section on the power saving function. stp mode the execution of the stp instruction stops the oscillation circuit and pll circuit. it also stops input clock fx in , system clock f sys , biu , cpu , and peripheral devices clocks f 1 to f 4096 , wf 32 and wf 512 in the l state, and divide clocks fx 16 to fx 128 in the h state. in the watchdog timer, fff 16 is automatically set. as shown in figure 98, any one of divide clocks fx 16 to fx 128 , which is selected by the watchdog timer clock source select bits at stp termination (bits 6 and 7 of the watchdog timer frequency select register), becomes the watchdog timer s clock source. in the stp mode, the a-d converter and watchdog timer, which uses peripheral devices clocks f 1 to f 4096 , wf 32 and wf 512 , are stopped. at this time, timers a and b operate only in the event counter mode, and serial i/o communication is active while an external clock is se- lected. the stp mode is terminated by acceptance of an interrupt request or reset, and the oscillation circuit and pll circuit restart their opera- tions. input clock fx in , system clock f sys , and peripheral devices clocks f 1 to f 4096 , wf 32 and wf 512 are also supplied. when the stp mode is terminated by reset, supply of biu and cpu starts immediately after the oscillation circuit and pll circuit restart their operations. therefore, the reset input must be raised h after the operation-stabilizing time for these circuits has passed. the following two modes are available in order to terminate the stp mode by an interrupt: (1) the watchdog timer is used in order to measure the period from the operation restart of the oscillation circuit and pll circuit until the supply start of biu and cpu. (2) the supply of biu and cpu is started immediately after the op- eration restart of the oscillation circuit and pll circuit. when the external clock input select bit (bit 1 of the particular func- tion select register 0) = 0 or the system clock select bit (bit 5 of the clock control register) = 1 , the watchdog timer will start counting mode wit system clock stop select bit at wit active (note 1) oscillation circuit operations of function while wit, stp modes 0 f sys , 1 , f 1 to f 4096 active stp wf 32 , wf 512 biu , cpu stopped ( l ) stopped ( l ) peripheral devices using f 1 to f 4096 , wf 32 , wf 512 timers a, b, serial i/o, a-d converter: operation is enabled. (watchdog timer: stopped.) timers a, b: operation is enabled only in the event counter mode. serial i/o: operation is enabled only while an external clock is selected. a-d converter: stopped. (watchdog timer: stopped.) stopped ( l ) stopped ( l ) stopped ( l ) active (note 1) 1 stopped ( l ) stopped ( l ) stopped ( l ) stopped timers a, b: operation is enabled only in the event counter mode. serial i/o: operation is enabled only while an external clock is selected. a-d converter: stopped. (watchdog timer: stopped.) pll circuit active (note 2) active (note 2) stopped notes 1: when the external clock input select bit = 1 , the oscillation circuit stops. also, clock input from pin x in is available. 2: when the pll operation enable bit = 0 , the pll circuit stops. table 17. microcomputer s operation in stp and wit modes
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 96 fig. 101 bit configuration of particular function select register 1 fig. 102 bit configuration of watchdog timer frequency select register 76543210 particular function select register 1 stp-instruction-execution status bit (note 1) 0: normal operation. 1: stp instruction has been executed. wit-instruction-execution status bit (note 1) 0: normal operation. 1: wit instruction has been executed. standby state select bit 0: external bus 1: programmable i/o port system clock stop select bit at wit (note 2) 0: in wait mode, system clock f sys is active. 1: in wait mode, system clock f sys is stopped. address output select bit 0: address changes depending on bus access. 1: address changes only at access to external address. timer b2 clock source select bit in event counter mode: 0: clock input from pin tb2 in is counted. 1: fx 32 (f(x in )/32) is counted. address 63 16 notes 1: at power-on reset, this bit becomes 0 . at hardware reset or software reset, this bit retains the value just before reset. even when 1 is written, the bit status will not change. 2: setting this bit to 1 must be performed just before execution of the wit instruction. also, after the wait state is terminated, this bit must be cleared to 0 immediately. 76543210 watchdog timer frequency select register watchdog timer frequency select bit 0 : select w f 512 1 : select w f 32 watchdog timer clock source select bits at stp termination 0 0 : fx 32 0 1 : fx 16 1 0 : fx 128 1 1 : fx 64 76543210 address 61 16 down with one of the above divide clocks, fx 16 to fx 128 , after the os- cillation circuit and pll circuit have been restarted their operations owing to an interrupt. the most significant bit of the watchdog timer reaching 0 , supply of biu and cpu restarts. on the other hand, when the external clock input select bit = 1 and the system clock select bit = 0 , supply of biu and cpu will restart immediately after the oscillation circuit has been restarted their op- erations owing to an interrupt. (in actual fact, after the selected one of the above divide clocks, fx 16 to fx 128 , has been changed from h to l , this supply will restart.)
97 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers wit mode when the wit instruction is executed with the system clock stop se- lect bit at wit (bit 3 of the particular function select register 1 in fig- ure 101) being 0 , biu , cpu , and divide clocks wf 32 and wf 512 are stopped in the l state. however, the oscillation circuit, pll circuit, input clock fx in , system clock f sys , 1 , and peripheral devices clock f 1 to f 4096 remain operating. therefore, biu and cpu are stopped, whereas timers a and b, serial i/o, and the a-d converter, which use the peripheral devices clocks f 1 to f 4096 , are still operating. note that the watchdog timer is stopped. on the other hand, when the wit instruction is executed with the system clock stop select bit at wit being 1 , the oscillation circuit, pll circuit, and input clock fx in are operating, while system clock f sys , biu , cpu , and peripheral devices clocks stop operating. as a result, the a-d converter and watchdog timer, which use peripheral devices clocks f 1 to f 4096 , wf 32 and wf 512 , are stopped. at this time, timers a and b operate only in the event counter mode, and serial i/o communication is active only while an external clock is selected. if the internal peripheral devices are not used in the wit mode, the latter is better because the current dissipation is more saved. note that the system clock stop select bit at wit is to be set to 1 immedi- ately before execution of the wit instruction and cleared to 0 im- mediately after the wit mode is terminated. the wit state is terminated by acceptance of an interrupt request, and then, supply of biu and cpu will restart. since the oscillation circuit, pll circuit, and clock input fx in are operating in the wit mode, an interrupt processing can be executed just after the wit mode termination.
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 98 power saving function the following functions can save the power dissipation of the whole system. (1) external bus fixation in standby state by setting the standby state select bit (bit 2 of the particular function select register 1) to 1 , in the stop or wait mode, the i/o pins of the external buses and bus control signals can be switched to program- mable i/o port pins. by setting these pins state with the correspond- ing port registers and port direction registers, unnecessary current will not flow between the microcomputer and external devices. as a result, in the stop or wait mode, the power dissipation of the whole system can be lowered. table 18 lists the correspondence between the external buses, bus control signals, and programmable i/o port pins. this function is valid only in the stop or wait mode. at termination of the stop or wait mode, the original function of external buses and bus control signals become valid. table 18. correspondence between external buses, bus control sig- nals, and programmable i/o port pins external buses, bus control signals a 0 to a 7 , a 8 to a 15 , a 16 to a 23 0 standby state select bit a 0 to a 7 , a 8 to a 15 , a 16 to a 23 1 d 0 to d 7 , d 8 to d 15 (note) d 0 to d 7 , d 8 to d 15 p10 0 to p10 7 , p11 0 to p11 7 , p0 0 to p0 7 p1 0 to p1 7 , p2 0 to p2 7 rd, blw, bhw rd, blw, bhw (note) p3 1 , p3 2 , p3 3 cs 0 cs 0 p9 0 note: when the external data bus width = 8 bits (byte = v cc level), this becomes a programmable i/o port pin, regardless of the standby state select bit s contents. (2) stop of system clock in wait mode in the wait mode, if the internal peripheral devices need not to oper- ate, the system clock stop select bit at wit (bit 3 of the particular function select register 1) = 1 , both of system clock f sys and periph- eral devices clock stop their operations, and the power dissipation can be saved. for details, refer to the section on the standby function. (3) stop of oscillation circuit when an externally-generated-stable clock is input to pin x in , the power dissipation can be saved if both of the following conditions are met: the external clock input select bit (bit 1 of the particular function select register 0) = 1 . the oscillation driver between pins x in and x out stops its operation. at this time, the output level at pin x out is fixed to h . when not us- ing a pll output clock, also, the supply of biu and cpu restarts their operations just after the microcomputers returns from the stop mode, owing to an interrupt request occurrence. therefore, an in- struction can be executed just after the termination of the stop mode. for details, refer to the section on the clock generating circuit and standby function. (4) disconnection from pin v ref when not using the a-d converter and d-a converter, by setting the v ref connection select bit (bit 6 of the a-d control register 1) to 1 , the resistor ladder network of the a-d converter will be disconnected from the reference voltage input pin (v ref ). in this case, no current flows from pin v ref to the resistor ladder network, and the power dis- sipation can be saved. note that, after the v ref connection select bit changes from 1 (v ref disconnected) to 0 (v ref connected), be sure that a waiting time of 1 s of more has passed before the a-d conversion starts. for details, refer to the sections on the a-d con- verter and d-a converter. (5) address output selection in the memory expansion mode or microprocessor mode, when the address output select bit (bit 4 of the particular function select regis- ter 1) becomes 1 , the unnecessary change of address pins state will be avoided, without output of an address at access to the inter- nal area. for details, refer to the section on the biu.
99 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers fig 103. block diagram of debug function address compare register 0 address compare register 1 debug control register 0 matching compare register matching compare register address matching detect circuit debug control register 1 internal data bus (db 0 to db 15 ) cpu bus (address) address matching detection interrupt debug function when the cpu fetches an instruction code, an interrupt request will be generated if a selected condition is satisfied, as a resultant of comparison between a specified address and the start address where the instruction code is stored (the contents of pg and pc). the decision whether this condition is satisfied or not is called ad- dress matching detection, and the interrupt generated by this detec- tion is called an address matching detection interrupt. (for interrupt vector addresses, refer to the section on interrupts.) in the address matching detection, a non-maskable interrupt routine is proceeded without execution of the original instruction which has been allocated to the target address. the debug function provides the following two modes: the address matching detection mode, which is used to avoid the area where program exists or modify a program. the out-of-address-area detection mode, which is used to detect a program runaway. figures 103 shows the block diagram of the debug function. figures 104 and 105 show the bit configurations of the debug control regis- ters 0, 1, and address compare registers 0,1, respectively. the detect condition select bits of the debug control register 0 can select one condition between the following 4 conditions. when the selected address condition is satisfied, an address matching detec- tion interrupt request will be generated: (1) address matching detection 0 the contents of pg and pc match with the address which has been set in the address compare register 0. (2) address matching detection 1 the contents of pg and pc match with the address which has been set in the address compare register 1. (3) address matching detection 2 the contents of pg and pc match with the address which has been set in either of the address compare register 0 or address compare register 1. (4) out-of-address-area detection the contents of pg and pc are less than the address which has been set in the address compare register 0 or larger than the ad- dress which has been set in the address compare register 1. by setting the detect enable bit of the debug control register 0 to 1 , an address matching detection interrupt request will be generated if any one of the above address conditions is satisfied. clearing the detect enable bit to 0 generates no interrupt request even if any of the above address conditions is satisfied. the address compare register access enable bit of the debug con- trol register 1 must be set to 1 by the instruction just before the ac- cess operation (read/write). then, this bit must be cleared to 0 (disabled) by the next instruction. while this bit = 0 , the address compare registers 0, 1 cannot be accessed. the address-matching-detection 2 decision bit of the debug control register 1 decides, whether the address which has been set in the address compare register 0 or 1 matches with the contents of pg, pc, when the address matching detection 2 is selected. the con- tents of this bit is invalid when address matching detection 0 or 1 is selected. in order to use the debug function to avoid the area where program exists or modify a program, perform the necessary processing within an address matching interrupt routine. as a result, the contents of pg, pc, ps at acceptance of an address matching detection inter- rupt request (i.e. the address at which an address matching detec- tion condition is satisfied) have been pushed on to the stack. if a return destination address after the interrupt processing is to be al- tered, rewrite the contents of the stack, and then return by the rti instruction. to use the debug function to detect a program runaway, set an ad- dress area where no program exists into the address compare regis- ters 0 and 1 by using the out-of-address-area detection. when the cpu fetches instruction codes from this address area and executes them, an address matching detection interrupt request will be gener- ated. the above debug function cannot be evaluated by a debugger, so that the debug function must not be used while a debugger is run- ning.
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 100 fig. 104 bit configuration of debug control register 0, 1 fig. 105 bit configuration of address compare register 0, 1 76543210 debug control register 0 detect condition select bits (note 1) 000: do not select. 001: address matching detection 0 010: address matching detection 1 011: address matching detection 2 100: do not select. 101: out-of-address-area detection 110: do not select. 111: do not select fix this bit to 0 (note 1) . detect enable bit (note 1) 0: detection disabled. 1: detection enabled. fix this bit to 0 (note 1) . 1 at read. address 66 16 76543210 debug control register 1 fix this bit to 0 (note 1) . 0 at read (note 1) . address compare register access enable bit (note 2) 0: disabled 1: enabled fix this bit to 1 when using the debug function. fix this bit to 0 (note 1) . while debugger is not used, 0 at read. while debugger is used, 1 at read. address-matching-detection 2 decision bit ? valid when address matching detection 2 is selected. 0: matches with the contents of the address compare register 0. 1: matches with the contents of the address compare register 1. 0 at read. address 67 16 0 0 0 0 1 0 1 0 notes 1: at power-on reset, these bits = 0 ; at hardware reset or software reset, these bits retain the value just before reset. 2: set this bit to 1 with the instruction just before the address compare register 0, 1 (addresses 68 16 to 6d 16 ) is accessed. and then, clear this bit to 0 with the instruction just after the access. 0 address compare register 0 address compare register 1 the address to be detected (in other words, the start address of instruction) is set here. address 68 16 , 69 16 , 6a 16 6b 16 , 6c 16 , 6d 16 (23) 7 (8) (15) (16) 0 7 0 7
101 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers notes 1: in the flash memory mode, the read/programming/erase operation cannot be performed for areas except for the internal flash memory area. 2: the boot rom area can be reprogrammed only in the flash memory parallel i/o mode. when the boot rom area is read out by the cpu, these addresses are shifted to addresses 00c000 16 ?0ffff 16 (byte addresses). 3: the reserved area for the serial programmer is assigned to addresses ffb0 16 ?fbf 16 (byte addresses). when the flash memory serial i/o mode is used, do not program to this area. 16 kbytes 001fff 16 boot rom area user rom area 32 kbytes 2 kbytes 8 kbytes 8 kbytes 01ffff 16 003fff 16 005fff 16 006000 16 007fff 16 00ffff 16 010000 16 008000 16 00ffff 16 001fff 16 002fff 16 003000 16 003fff 16 007fff 16 008000 16 004000 16 003800 16 004000 16 001c00 16 002000 16 byte address word address 000000 16 003fff 16 000000 16 byte addresses word addresses 64 kbytes total 498 kbytes 64 kbytes 64 kbytes 02ffff 16 020000 16 017fff 16 010000 16 03ffff 16 030000 16 01ffff 16 018000 16 64 kbytes 04ffff 16 040000 16 027fff 16 020000 16 64 kbytes 05ffff 16 050000 16 02ffff 16 028000 16 64 kbytes 06ffff 16 060000 16 037fff 16 030000 16 64 kbytes 07ffff 16 070000 16 03ffff 16 038000 16 flash memory mode these microcomputers contain the dinor (divided bit line nor)- type flash memory; and single-power-supply reprogramming is avail- able to this. these microcomputers have the following three modes, enabling reading/programming/erasure for the flash memory: ?flash memory parallel i/o mode and flash memory serial i/o mode, where the flash memory is handled by using an external pro- grammer. ?cpu reprogramming mode, where the flash memory is handled by the central processing unit (cpu). as shown in figures 106 to 108, the flash memory is divided into several blocks, and erasure per block is possible. each of these blocks is provided with a lock bit, which determines the validity of erasure/program execution. therefore, data protection per fig 106. m37902fjchp: block configuration of internal flash memory block is possible. this internal flash memory has the boot rom area storing the repro- gramming control software for reprogramming in the cpu repro- gramming mode and flash memory serial i/o mode, as well as the user rom area storing a certain control software for the normal op- eration in the microcomputer mode. although our reprogramming control firmware for the flash memory serial i/o mode has been stored into this boot rom area on ship- ment, the user-original reprogramming control software which is more appropriate for the users system is reprogrammable into this area, instead. note that the reprogramming for the boot rom area is enabled only in the flash memory parallel i/o mode.
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 102 fig 108. m37902fgchp: block configuration of internal flash memory notes 1: in the flash memory mode, the read/programming/erase operation cannot be performed for areas except for the internal flash memory area. 2: the boot rom area can be reprogrammed only in the flash memory parallel i/o mode. when the boot rom area is read out by the cpu, these addresses are shifted to addresses 00c000 16 00ffff 16 (byte addresses). 3: the reserved area for the serial programmer is assigned to addresses ffb0 16 ffbf 16 (byte addresses). when the flash memory serial i/o mode is used, do not program to this area. 16 kbytes 001fff 16 boot rom area user rom area 32 kbytes 8 kbytes 8 kbytes 8 kbytes 01ffff 16 003fff 16 005fff 16 006000 16 007fff 16 00ffff 16 010000 16 008000 16 00ffff 16 001fff 16 002fff 16 003000 16 003fff 16 007fff 16 008000 16 004000 16 002000 16 004000 16 001000 16 002000 16 byte address word address 000000 16 003fff 16 000000 16 byte addresses word addresses 64 kbytes total 248 kbytes 64 kbytes 64 kbytes 02ffff 16 020000 16 017fff 16 010000 16 03ffff 16 030000 16 01ffff 16 018000 16 fig 107. m37902fcchp: block configuration of internal flash memory 16 kbytes 001fff 16 boot rom area user rom area 32 kbytes 8 kbytes 8 kbytes 8 kbytes 01ffff 16 003fff 16 005fff 16 006000 16 007fff 16 00ffff 16 010000 16 008000 16 00ffff 16 001fff 16 002fff 16 003000 16 003fff 16 007fff 16 008000 16 004000 16 002000 16 004000 16 001000 16 002000 16 byte address word address 000000 16 003fff 16 000000 16 byte addresses word addresses 64 kbytes total 120 kbytes notes 1: in the flash memory mode, the read/programming/erase operation cannot be performed for areas except for the internal flash memory area. 2: the boot rom area can be reprogrammed only in the flash memory parallel i/o mode. when the boot rom area is read out by the cpu, these addresses are shifted to addresses 00c000 16 00ffff 16 (byte addresses). 3: the reserved area for the serial programmer is assigned to addresses ffb0 16 ffbf 16 (byte addresses). when the flash memory serial i/o mode is used, do not program to this area.
103 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers flash memory parallel i/o mode the flash memory parallel i/o mode is used to manipulate the inter- nal flash memory with a parallel programmer. this parallel program- mer uses the software commands listed in table 19 to do the flash memory manipulations, such as read/programming/erase opera- tions. in the flash memory parallel i/o mode, each block can be protected from erasing/programming (in other words, block lock). table 19. software commands (flash memory parallel i/o mode) software command read array read status register clear status register page programming (note) block erase erase all unclocked block lock bit programming read lock bit status note: programming is performed in a unit of 256 bytes, with the low-order address assigned in the range of 00 16 ff 16 (byte addresses). user rom area and boot rom area the user rom area and boot rom area can be reprogrammed in the flash memory parallel i/o mode. the programming and block erase operations can be performed only to these areas. the boot rom area, 16 kbytes in size, is assigned to addresses 0000 16 3fff 16 (byte addresses), so that programming and block erase operations can be performed only to this area. (access to any address out of this area is prohibited). the erasable block in the boot rom area is only one block, consist- ing of 16 kbytes. the reprogramming control firmware to be used in the flash memory serial i/o mode has been stored to this boot rom area on our shipment. therefore, do not reprogram the boot rom area if the user uses the flash memory serial i/o mode. addresses ffb0 16 to ffbf 16 are the reserved area for the serial programmer. therefore, when the user uses the flash memory serial i/o mode, do not program to this area. note that, when the boot rom area is read out from the cpu in the cpu reprogramming mode, described later, its addresses will be shifted to c000 16 ffff 16 (byte addresses).
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 104 flash memory serial i/o mode in the flash memory serial i/o mode, addresses, data, and software commands, which are required to read/program/erase the internal flash memory, are serially input and output with a fewer pins and the dedicated serial programmer. in this mode, being different from the flash memory parallel i/o mode, the cpu controls reprogramming of the flash memory (using the cpu reprogramming mode), serial input of the reprogramming data, etc. the reprogramming control firmware for the flash memory serial i/o mode has been stored in the boot rom area on shipment of the product from us. note that, then, the flash memory serial i/o mode will become unavailable if the boot rom area has been repro- grammed in the flash memory parallel i/o mode. note that, also, this reprogramming control firmware for the flash memory serial i/o mode is subject to change. figure 112 shows the pin connection in the flash memory serial i/o mode. the three pins, sclk, sda, and busy, are used to input and output serial data. the sclk pin is the input pin of external transfer clocks. the sda pin is the i/o pin of transmit and receive data, and its output acts as the n-channel open-drain output. to the sda pin, connect an exter- nal pullup resistor (about 1 k ? h during busy periods owing to a certain operation, such as transmit, receive, erase, program- ming, etc. transmit and receive data are serially transferred 8 bits at a time. in the flash memory serial i/o mode, only the user rom area can be reprogrammed; the boot rom area is not accessible. addresses ffb0 16 to ffbf 16 are the reserved area for the serial programmer. therefore, when the user uses the flash memory serial i/o mode, do not program to this area.
105 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers fig.112 pin connection of m37902fxchp in flash memory serial i/o mode output 100p6q-a p4 1 / ? ?
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 106 cpu reprogramming mode the cpu reprogramming mode is used to perform the operations for the internal flash memory (reading, programming, erasing) under control of the cpu. in this mode, only the user rom area can be reprogrammed; the boot rom area cannot be reprogrammed. the user-original reprogramming control software for the cpu repro- gramming mode can be stored in either the user rom area or the boot rom area. because the cpu cannot read out the flash memory in the cpu reprogramming mode, the above software must be trans- ferred to the internal ram in advance to be executed. boot mode the user-original reprogramming control software for the cpu re- programming mode must be stored into the user rom area or the boot rom area in the flash memory parallel i/o mode in advance. (if this program has been stored into the boot rom area, the flash memory serial i/o mode will become unavailable). note that addresses of the boot rom area depend on the accessing ways to the boot rom area, when accessing in the flash memory parallel i/o mode, these addresses will be shifted to 0000 16 to 3fff 16 (byte address). on the other hand, when accessing with the cpu, these addresses will be shifted to c000 16 to ffff 16 (byte address). reset removal with both of the md0 and md1 pins held ??invokes the normal microcomputer mode, and the cpu operates using the control software stored in the user rom area. in this case, the boot rom area is not accessible. removing reset with the md0 pin held ??and the md1 pin ?? the cpu starts its operation using the reprogramming control software stored in the boot rom area. this mode is called the boot mode. the reprogramming control software in the boot rom area can also re- program the user rom area. after reset removal, be sure not to change the status at pins md0 and md1. fig. 114 bit configuration of flash memory control register flash memory control register ry/by status bit 0: busy (programming or erasing is active.) 1: ready cpu reprogramming mode select bit (note 2) 0: normal mode (software commands are ignored.) 1: cpu reprogramming mode (software commands are acceptable.) lock bit invalidity select bit (note 3) 0: block lock by lock bit data is valid. 1: block lock by lock bit data is invalid. flash memory reset bit (note 4) 0: normal operation 1: reset must be 0 . user rom area select bit (note 5) (valid only in the boot mode.) 0: boot rom area access 1: user rom area access address 9e 16 76543210 0 notes 1: the contents of the flash memory control register after reset is removed are xx000001 2 . 2: to set 1 , writing of 0 to bit 1 and subsequent writing of 1 to bit 1 are necessary. writing to bit 1 must be performed by the user-original reprogramming control software in the internal ram. 3: to set 1 , writing of 0 to bit 2 and subsequent writing of 1 to bit 2 are necessary while bit 1 = 1 . 4: valid only when bit 1 = 1 . set bit 3 to 1 (reset), and then clear to 0 . this bit 3 must be controlled with bit 1 = 1 . 5: writing to bit 5 must be performed by the user-original reprogramming control software in the internal ram.
107 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers function overview (cpu reprogramming mode) the cpu reprogramming mode is available in the single-chip mode, memory expansion mode, and boot mode to reprogram the user rom area only. in the cpu reprogramming mode, the cpu erases, programs, and reads the internal flash memory by writing software commands. note that the user-original reprogramming control software must be trans- ferred to the internal ram in advance to be executed. the cpu reprogramming mode becomes active when 1 is written into the flash memory control register s bit 1 (the cpu reprogram- ming mode select bit) shown in figure 114, and software commands become acceptable. in the cpu reprogramming mode, software commands and data are all written to and read from even addresses (note that address a 0 in byte addresses = 0 .) 16 bits at a time. therefore, a software com- mand consisting of 8 bits must be written to an even address; there- fore, any command written to an odd address will be invalid. since the write data at the 2nd cycle of a programming command consists of 16 bits, this data must be written to even and odd addresses. the write state machine (wsm) in the flash memory controls the erase and programming operations. what the status of the wsm operation is and whether the programming or erase operation has been completed normally or terminated by an error can be examined by reading the status register. figure 114 shows the bit configuration of the flash memory control register. bit 0 (the ry/by status bit) is a read-only bit for indicating the wsm operation. this bit goes to 0 (busy) while the automatic program- ming/erase operation is active and goes to 1 (ready) during the other operations. bit 1 serves as the cpu reprogramming mode select bit. writing of 1 to this bit selects the cpu reprogramming mode, and software commands will be acceptable. because the cpu cannot directly ac- cess the internal flash memory in the cpu reprogramming mode, writing to this bit 1 must be performed by the user-original repro- gramming control software which has been transferred to the inter- nal ram in advance. to set bit 1 to 1 , it is necessary to write 0 and 1 to this bit 1 successively. on the other hand, to clear this bit to 0 , it is sufficient only to write 0 . bit 2 serves as the lock bit invalidity select bit, and setting this bit to 1 invalidates the protection by a lock bit against erasing and pro- gramming (block lock). the lock bit invalidity select bit can invali- dates the lock bit function but set no lock bit itself. however, if erasing is performed with this bit = 1 , a lock bit with value 0 (the locked state) will be set to 1 (the unlocked state) after the erasing has been completed. to set the lock bit invalidity select bit to 1 , write 0 and 1 to this bit 2 successively with the cpu reprogramming mode select bit = 1 . the manipulation of bit 2 is allowed only when the cpu reprogramming mode select bit = 1 . bit 3 (the flash memory reset bit) resets the control circuit of the in- ternal flash memory and is used when the cpu reprogramming mode is terminated or when an abnormal access to the flash memory happens. writing of 1 to bit 3 with the cpu reprogramming mode select bit = 1 preforms the reset operation. to remove the reset, write 0 to bit 3 subsequently. bit 5 serves as the user rom area select bit and is valid only in the boot mode. setting this bit to 1 in the boot mode switches an acces- sible area from the boot rom area to the user rom area. to use the cpu reprogramming mode in the boot mode, set this bit to 1 . note that when the microcomputer is booted up in the user rom area, only the user rom area is accessible and bit 5 is invalid; on the other hand, when the microcomputer is in the boot mode, bit 5 is valid in- dependent of the cpu reprogramming mode. to rewrite bit 5, ex- ecute the user-original reprogramming control software transferred to the internal ram in advance. figure 115 shows the cpu reprogramming mode set/termination flowchart, and be sure to follow this flowchart. as shown in note 1 of figure 115, before selecting the cpu reprogramming mode, set the processor mode register 1 s bit 7 (the internal rom bus cycle select bit) to 0 and set flag i to 1 to avoid an interrupt request input. when an nmi interrupt or a watchdog timer interrupt request is gen- erated in the cpu reprogramming mode, when an input to the reset pin is l , or when the software reset is performed, the flash memory control circuit and flash memory control register will be re- set. when the flash memory is reset during the erase or programming operation, this operation is cancelled and the target block s data will be invalid. just before writing a software command related to the erase/programming operation, be sure to write to the watchdog timer. also, be sure to set the nmi pin to h to avoid an nmi interrupt request occurrence. in the cpu reprogramming mode, be sure not to use the stp and wit instructions.
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 108 fig. 115 cpu reprogramming mode set/termination flowchart software commands table 20 lists the software commands. by writing a software command after the cpu reprogramming select bit has been set to ?? erasing, programming, etc. can be specified. note that, at software commands?input, the high-order byte (d 8 d 15 ) is ignored. (except for the write data at the 2nd cycle of a page programming command.) software commands are explained as below. read array command (ff 16 ) by writing command code ?f 16 ?at the 1st bus cycle, the microcom- puter enters the read array mode. if an address to be read is input in the next or the following bus cycles, the contents at the specified ad- dress are output to the data bus (d 0 to d 15 ) in a unit of 16 bits. the read array mode is maintained until writing of another software command. read status register command (70 16 ) writing command code ?0 16 ?at the 1st bus cycle outputs the con- tents of the status register to the data bus (d 0 -d 7 ) by a read at the 2nd bus cycle. the status register is explained later. clear status register command (50 16 ) this command clears three status bits (sr.3?) each of which is set to ??to indicate that the operation has been terminated by an error. to clear these bits, write command code ?0 16 ?at the 1st bus cycle. page programming command (41 16 ) page programming facilitates quick programming of 128 words (a page = 256 bytes) at a time. to initiate page programming, write command code ?1 16 ?at the 1st bus cycle; then, program a series of data, in a unit of 16 bits, sequentially from the 2nd to the 129th bus cycle. it is necessary, at this time, to increment address a 0 ? 7 from "00 16 " to ?e 16 ?by +2. (programmed to even addresses.) upon completion of data loading, automatic programming (data pro- gramming and verification) operation is started. the completion of the automatic programming operation is recog- nized by a read of the status register or a read of the flash memory control register. as the automatic programming operation starts, the microcomputer enters the read status register mode automatically to allow reading out the contents of the status register. bit 7 of the sta- tus register (sr.7) is cleared to ??simultaneously with the start of the automatic programming operation; and also, bit 7 returns to ? by the end of it. until writing of the read array command (ff 16 ), writ- ing of the read lock bit status command (71 16 ), or performing the re- set operation with the flash memory reset bit, this read status register mode is maintained. in continuous programming, if there is no pro- gramming error, page programming commands can be executed with the read status register mode kept. completed start read array command is executed, or reset is performed by setting the flash memory reset bit. (writing of 1 writing of 0 ) (note 2) single-chip mode, memory expansion mode, or boot mode the processor mode register 1 is set (note 1) . flag i is set to 1 . operations such as erasing, programming are executed by using software commands. (if necessary, the lock bit invalidity select bit is set.) jump to the above software in the internal ram. (the operations shown below will be executed by the above software in this ram.) the user-original reprogramming control software for the cpu reprogramming mode is transferred to the internal ram. (only in the boot mode.) writing of 0 to user rom area select bit (note 3) . writing of 0 to the cpu reprogramming mode select bit. (only in the boot mode.) the user rom area select bit is set to 1 . writing of 1 to the cpu reprogramming mode select bit. (writing of 0 writing of 1 ) notes 1: the processor mode register 1 s bit 7 (address 5f 16 , the internal rom bus cycle select bit) must be 0 (bus cycle = 3 ). 2: to terminate the cpu reprogramming mode after the erase and programming operations have been completed, be sure to execute the read array command or perform the flash memory reset operation. 3: this bit may remain 1 . however, if this bit is 1 , the user rom area access is specified.
109 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers table 20. software commands (cpu reprogramming mode) command read array read status register clear status register page programming (note 3) block erase erase all unclocked block lock bit programming read lock bit status address x (note 2) x x x x x x x ff 16 70 16 50 16 41 16 20 16 a7 16 77 16 71 16 1st cycle 2nd cycle notes 1: at software commands input, the high-order byte of data (d 8 d 15 ) is ignored. 2: x = an arbitrary address in the user rom area. (note that a 0 = 0 .) 3: srd = status register data. 4: wa = write address, wd = write data (16 bits). wa and wd must be set from 00 16 to fe 16 . (byte addresses. incremented by +2. address a 0 = 0 .) page size = 128 words (128 16 bits). 5: block address: the maximum address of each block must be input. note that address a 0 = 0 . 6: d 6 indicates the block lock status. 1 = unlocked. 0 = locked. mode write write write write write write write write 3rd cycle (d 0 to d 7 ) data address x wa0 (note 4) ba (note 5) x ba ba srd (note 3) wd0 (note 4) d0 16 d0 16 d0 16 d 6 (note 6) mode read write write write write read data address wa1 mode write the ry/by status bit of the flash memory control register goes 0 during the automatic programming operation; and also, it goes 1 af- ter the end of it, the same way as bit 7 of the status register. before execution of the next command, be sure to verify that bit 7 of the status register (sr.7) or the ry/by status bit is set to 1 (ready). during the automatic programming operation, writing of commands and access to the flash memory must not be performed. reading out the status register after the automatic programming op- eration is completed reports the result of it. for details, refer to the section on the status register. figure 116 shows an example of the page programming flowchart. note that each block can be protected from programming by using a lock bit. for details, refer to the section on the data protect function. additional programming to any page that has already been pro- grammed is prohibited. block erase command (20 16 /d0 16 ) writing command code 20 16 at the 1st bus cycle and writing verify command code d0 16 and the maximum address of the block (note that address a 0 = 0 .) at the subsequent 2nd bus cycle initiate the automatic erase (erasing and erase verification) operation for the specified block. the completion of the automatic erase operation is verified by a read of the status register or a read of the flash memory control register. as the automatic erase operation starts, the microcomputer enters the read status register mode automatically to allow reading out the contents of the status register. bit 7 of the status register (sr.7) is cleared to 0 simultaneously with the start of the automatic erase operation; and also, it returns to 1 by the end of it. the read status register mode is maintained until writing of the read array command (ff 16 ), writing of the read lock bit status command (71 16 ), or per- forming the reset operation with the flash memory reset bit. the ry/by status bit of the flash memory control register goes 0 during the automatic erase operation; and also, it goes 1 after the end of it, the same way as bit 7 of the status register. before execution of the next command, be sure to verify that bit 7 of data wd1 the status register (sr.7) or the ry/by status bit is set to 1 (ready). during the automatic erase operation, writing of com- mands and access to the flash memory must not be performed. reading out the status register after the automatic erase operation is completed reports the result of it. for details, refer to the section on the status register. figure 117 shows an example of the block erase flowchart. note that each block can be protected from erasing by using a lock bit. for details, refer to the section on the data protect function.
mitsubishi microcomputers m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer 110 fig. 116 page programming flowchart fig. 117 block erase flowchart fig. 119 read lock bit status flowchart fig. 118 lock bit programming flowchart n = fe 16 start write 41 16 n = 0 write address n , data n sr.7 = 1? status register read full status check page programming completed n = n + 2 no yes no yes write 20 16 write d0 16 status register read sr.7 = 1? full status check block erase completed no yes block address start sr.7 = 1? write 77 16 write d0 16 no yes sr.4 = 0? no lock bit programming completed block address lock bit programming error yes start block: unlocked write 71 16 d 6 = 0? block: locked no yes block address start
111 mitsubishi microcomputers m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer erase all unlocked block command (a7 16 /d0 16 ) writing command code ?7 16 ?at the 1st bus cycle and writing verify command code ?0 16 ?at the subsequent 2nd bus cycle initiate the continuous block erase (chip erase) operations for all the blocks. the completion of the chip erase operation, as well as of the block erase operation, is verified by a read of the status register or a read of the flash memory control register. the result of the automatic erase operation is also reported by a read of the status register. during the automatic erase operation (when the ry/by status bit = ??, writing of commands and access to the flash memory must not be performed. when the lock bit invalidity select bit = ?? all the blocks are erased regardless of the status of their lock bits. when the lock bit invalidity select bit = ?? on the contrary, the status of each lock bit becomes valid, so only the blocks in the unlocked state (lock bit = ?? are erased. lock bit programming command (77 16 /d0 16 ) by writing of command code ?7 16 ?at the 1st bus cycle and writing of verify command code ?0 16 ?and the blocks maximum address (note that address a 0 = ??) at the subsequent 2nd bus cycle, ? (the locked state) is written into the lock bit of the specified block. figure 118 shows an example of the lock bit programming flowchart. the status of the lock bit can be read out by the read lock bit status command. the completion of the lock bit programming operation, as well as of the page programming operation, is verified by a read of the status register or a read of the flash memory control register. for details of the lock bits function and the method of reset, refer to the section on the data protect function. read lock bit status command (71 16 ) by writing of command code ?1 16 ?at the 1st bus cycle and writing of the blocks maximum address (note that address a 0 = ??) at the subsequent 2nd bus cycle, the status of the lock bit of the specified block is output to the data bus (d 6 ). figure 119 shows an example of the read lock bit programming flowchart. data protect function (block lock) each block is implemented with a nonvolatile lock bit to protect the block from erasing/programming (block lock). a ??(the locked state) can be written to a lock bit using the lock bit programming command, and the lock bit of each block can be read out by using the read lock bit status command. whether a block lock is valid or invalid is determined by the status of the lock bit and the lock bit invalidity select bit of the flash memory control register. (1) when the lock bit invalidity select bit = ?? a lock bit determines whether to lock or unlock the corresponding block. a block with its lock bit = ??is locked and inhibited from erasing and pro- gramming. on the other hand, a block with its lock bit = ??re- mains unlocked and allows to be erased/programmed. (2) when the lock bit invalidity select bit = ?? all the blocks are un- locked and allows to be erased/programmed regardless of the values of their lock bits. in this case, a lock bit with a value ? (the locked state) is set to ??(the unlocked state) after completion of the erase operation, and the locked state by the lock bit is terminated. to perform erase or programming, be sure to do one of the following. ?by executing the read lock bit status command, verify that the lock of the target block is invalid. ?set the lock bit invalidity select bit to ??to invalidate the lock. when the block erase or programming is performed with the lock valid, the erase status bit (sr.5) and programming status bit (sr.4) are set to ??(terminated by error). status register the status register is used to indicate what the status of the write state machine (wsm) operation is and whether the programming/ erase operation has been completed normally or terminated by an error. by writing the read status register command (70 16 ), the con- tents of the status register can be read out; by writing the clear sta- tus register command (50 16 ), the contents of the status register can be cleared. table 21 lists the definition of each bit of the status register. the status register outputs ?0 16 ?after reset is removed. the status of each bit is described below.
mitsubishi microcomputers m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer 112 busy terminated normally. terminated normally. terminated normally. ready terminated by error. terminated by error. terminated by error. table 21. bit definition of status register sr.7 (d 7 ) sr.6 (d 6 ) sr.5 (d 5 ) sr.4 (d 4 ) sr.3 (d 3 ) sr.2 (d 2 ) sr.1 (d 1 ) sr.0 (d 0 ) write state machine (wsm) status reserved erase status programming status block status after programming reserved reserved reserved symbol status definition ? ? write state machine (wsm) status bit (sr.7) this bit reports the operation status of the wsm. this bit is set to ? (ready) after the system power is turned on or after reset is re- moved. during the automatic programming or erase operation, this bit is cleared to ??(busy), however, set to ??upon completion of them. erase status bit (sr.5) this bit reports the status of the automatic erase operation. this bit is set to ??if an erase error occurs and returns to ??if one of the following conditions is satisfied: ?the system power is turned on. ?reset is removed. ?the clear status register command (50 16 ) is executed. programming status bit (sr.4) this bit reports the status of the automatic programming operation. this bit is set to ??if a programming error occurs and returns to ? if one of the following conditions is satisfied: ?the system power is turned on. ?reset is removed. ?the clear status register command (50 16 ) is executed. block status after programming bit (sr.3) this bit is set to ?? upon completion of the page programming op- eration, if the excessive programming (note) occurs. that is, the sta- tus register becomes ?0 16 ?when the programming operation is terminated normally, ?0 16 ?when the programming operation is failed, and ?8 16 ?when the excessive programming occurs. under the condition that any of sr.5, sr.4 and sr.3 = ?? none of the page programming, block erase, erase all unlocked block, and lock bit programming commands can be accepted. to execute these commands, in advance, execute the clear status register command (50 16 ) to clear the status register. both of sr.4 and sr.5 are set to ??under the following conditions (command sequence error): (1) when data other than ?0 16 ?and ?f 16 ?is written to the data in the 2nd bus cycle of the lock bit programming command (77 16 / d0 16 ) (2) when data other than ?0 16 ?and ?f 16 ?is written to the data in the 2nd bus cycle of the block erase command (20 16 /d0 16 ) (3) when data other than ?0 16 ?and ?f 16 ?is written to the data in the 2nd bus cycle of the erase all unlocked block command (a7 16 /d0 16 ) note that, writing of ?f 16 ?forces the microcomputer into the read array mode. simultaneously with this, the command written in the 1st bus cycle will be canceled. note: the excessive programming means the status that memory cells are too depleted, so data cannot be read out correctly. full status check the full status check reports the results of the erase or programming operation. figure 120 shows the full status check flowchart and actions to be taken if an error has occurred.
113 mitsubishi microcomputers m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer fig. 120 full status check flowchart and actions to be taken if an error has ocurred status register read sr.4 = 1 no command sequence error yes sr.5 = 0? yes block erase error no sr.4 = 0? yes programming error (page, lock bit) no sr.3 = 0? yes programming error (block) no end (block erase, programming) and sr.5 = 1 ? execute the clear status register command (50 16 ) to clear the status register. after verifying the command to be correctly input, start the operation again. examine whether a lock is active or not by executing the read lock bit status command (71 16 ). after removing the lock, perform block erase again. if the same error still occurs, this page cannot be used. examine whether a lock is active or not by executing the read lock bit status command (71 16 ). after removing the lock, perform programming again. if the same error still occurs, this page cannot be used. after erasing the block where an error has occured, perform programming again. if the same error still occurs, this block cannot be used. note: under the condition that any of sr.5, sr.4 and sr.3 = 1 , none of the page programming, block erase, erase all unlocked block, and lock bit programming commands can be accepted. to execute these commands, in advance, execute the clear status register command (50 16 ). ac electrical characteristics (v cc = 5 v ?0.5 v, ta = 0 to 60 ?, f(f sys ) = 26 mhz (note)) the limits of parameters other than the above are same as those in the microcomputer mode. note: f(f sys ) indicates the system clock (fsys) frequency. symbol parameter limits unit i cc1 i cc2 i cc3 i cc4 min. typ. max. v cc power source current (at read) v cc power source current (at write) v cc power source current (at programming) v cc power source current (at erasing) 30 48 48 54 54 dc electrical characteristics (v cc = 5 v ?0.5 v, ta = 0 to 60 ?, f(f sys ) = 26 mhz (note)) limits of v ih , v il , v oh , v ol , i ih , and i il for each pin are the same as those in the microcomputer mode. note: f(f sys ) indicates the system clcok (fsys) frequency. ma ma ma ma parameter page programming time block erase time erase all unlocked block time lock bit programming time limits unit min. typ. max. 8 50 50 ? n 8 120 600 600 ? n 120 ms ms ms ms n = number of blocks to be erased
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 114 unit v v v v v v v v v v v v v v v v v v ma ma ma ma mhz mhz max. 5.5 vcc v cc vcc vcc vcc vcc vcc 0.2 v cc 0.2 v cc 0.2 v cc 0.16 v cc 0.16 v cc 0.16 v cc 0.16 v cc ?0 ? 10 5 26 26 parameter power source voltage analog power source voltage power source voltage analog power source voltage high-level input voltage x in , reset, byte, md0, md1 high-level input voltage p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 3 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 7 , p10 0 ?10 7 , p11 0 ?11 7 high-level input voltage p0 0 ?0 7 (when the port p0 input level select bit = ?? high-level input voltage p0 0 ?0 7 (when the port p0 input level select bit = ?? high-level input voltage d 0 ? 7 , d 8 ? 15 high-level input voltage rdy, hold, ta0 in ?a4 in , ta0 out ?a4 out , tb0 in ?b2 in , ki 0 ?i 3 , int 0 ?nt 4 , nmi, ad trg , cts 0 , cts 1 , clk 0 , clk 1 , rxd 0 , rxd 1 high-level input voltage sclk, sda (note 1) low-level input voltage x in , reset, byte, md0, md1 low-level input voltage p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 3 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 7 , p10 0 ?10 7 , p11 0 ?11 7 low-level input voltage p0 0 ?0 7 (when the port p0 input level select bit = ?? low-level input voltage p0 0 ?0 7 (when the port p0 input level select bit = ?? low-level input voltage d 0 ? 7 , d 8 ? 15 low-level input voltage rdy, hold, ta0 in ?a4 in , ta0 out ?a4 out , tb0 in ?b2 in , ki 0 ?i 3 , int 0 ?nt 4 , nmi, ad trg , cts 0 , cts 1 , clk 0 , clk 1 , rxd 0 , rxd 1 low-level input voltage sclk, sda (note 1) high-level peak output current p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 3 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 7 , p10 0 ?10 7 , p11 0 ?11 7 high-level average output current p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 3 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 7 , p10 0 ?10 7 , p11 0 ?11 7 low-level peak output current p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 3 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 7 , p10 0 ?10 7 , p11 0 ?11 7 low-level average output current p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 3 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 7 , p10 0 ?10 7 , p11 0 ?11 7 external clock input frequency (note 2) system clock frequency symbol v cc av cc v ss av ss v ih v ih v ih v ih v ih v ih v ih v ih v il v il v il v il v il v il i oh(peak) i oh(avg ) i ol(peak) i ol(avg) f(x in ) f(f sys ) parameter power source voltage analog power source voltage input voltage p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 3 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 7 , p10 0 ?10 7 , p11 0 ?11 7, v ref , x in , reset, byte, md0, md1, nmi, v cont output voltage p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 3 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 7 , p10 0 ?10 7 , p11 0 ?11 7 , x out power dissipation operating ambient temperature storage temerature symbol v cc av cc v i v o p d t opr t stg absolute maximum ratings recommended operating conditions (vcc = 5 v, ta = ?0 to 85 ?, unless otherwise noted) notes 1: pins sclk and sda are used only in the flash memory serial i/o mode. 2: when using the pll frequency multiplier, be sure that f(f sys ) = 26 mhz or less. 3: average output current is the average value of an interval of 100 ms. 4: the sum of i ol(peak) for ports p0?2, p8, p10, and p11 must be 80 ma or less, the sum of i oh(peak) for ports p0?2, p8, p10, and p11 must be 80 ma or less, the sum of i ol(peak) for ports p3?7 must be 80 ma or less, the sum of i oh(peak) for ports p3?7 must be 80 ma or less. unit v v v v mw ? ? ratings ?.3 to 6.5 ?.3 to 6.5 ?.3 to v cc +0.3 ?.3 to v cc +0.3 400 ?0 to 85 ?0 to 150 limits min. 4.5 0.8 vcc 0.7 v cc 0.7 vcc 0.43 vcc 0.43 vcc 0.43 vcc 0.43 vcc 0 0 0 0 0 0 0 typ. 5.0 v cc 0 0
115 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers unit v v v v v v v v v a a a ma v ma a f(f sys ) = 26 mhz. cpu operates. ta = 25 c when clock is stopped. ta = 85 c when clock is stopped. test conditions i oh = ?0 ma i oh = ?00 a i oh = ?0 ma i oh = ?00 a i ol = 10 ma i ol = 2 ma i ol = 10 ma i ol = 2 ma v i = 5.0 v v i = 0 v v i = 0 v, no pullup transistor v i = 0 v, pullup transistor used when clock is stoped. parameter high-level output voltage p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 7 , p10 0 ?10 7 , p11 0 ?11 7 high-level output voltage p0 0 ?0 7, p1 0 ?1 7 , p2 0 ?2 7 , p4 0 , p4 2 , p4 4 ?4 7 , p10 0 ?10 7 , p11 0 ?11 7 high-level output voltage p3 1 ?3 3 low-level output voltage p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 7 , p10 0 ?10 7 , p11 0 ?11 7 low-level output voltage p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p4 0 , p4 2 , p4 4 ?4 7 , p10 0 ?10 7 , p11 0 ?11 7 low-level output voltage p3 1 ?3 3 hysteresis rdy, hold, ta0 in ?a4 in , ta0 out ?a4 out , tb0 in ?b2 in , ki 0 ?i 3 , int 0 ?nt 4 , nmi, ad trg , cts 0 , cts 1 , clk 0 , clk 1 , rxd 0 , rxd 1 hysteresis reset hysteresis x in high-level input current p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 3 , p4 0 ?4 7 , p5 0 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 7 , p10 0 ?10 7 , p11 0 ?11 7 , x in , reset, byte, md0, md1, nmi low-level input current p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 3 , p4 0 ?4 3 , p5 0 ?5 3 , p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 7 , p10 0 ?10 7 , p11 0 ?11 7 , x in , reset, byte, md0, md1 low-level input current p4 4 ?4 7 , p5 4 ?5 7 , nmi ram hold voltage power source current symbol v oh v oh v oh v ol v ol v ol v t+ vt v t+ vt v t+ vt i ih i il i il v ram i cc dc electrical characteristics (vcc = 5 v, vss = 0 v, ta = ?0 to 85 ?, f(f sys ) = 26 mhz (note) ) min. 3 4.7 3.4 4.8 0.2 0.5 0.1 ?.4 2 limits typ. ?.7 30 max. 2 0.45 1.6 0.4 0.7 1.5 0.3 5 ? ? ?.1 54 1 20 output-only pins are open, and the other pins are con- nected to vss or vcc. an external square-waveform clock is input. (pin x out is open.) the pll frequency multiplier stops its operation.
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 116 resolution absolute accuracy ladder resistance conversion time reference voltage analog input voltage r ladder t conv v ref v ia v ref = v cc v ref = v cc v ref = v cc f(f sys ) 26 mhz max. a-d converter characteristics (v cc = av cc = 5 v ?0.5 v, v ss = av ss = 0 v, t a = ?0 to 85 ?, unless otherwise noted) unit parameter symbol test conditions limits min. 10-bit resolution mode 8-bit resolution mode 10-bit resolution mode 8-bit resolution mode 5 4.54 1.89 (note) 2.7 0 10 ?3 ?2 v cc v ref bits lsb lsb k ? s v v note: this is applied when a-d conversion freguency ( ad ) = f 1 . d-a converter characteristics (v cc = 5 v, v ss = av ss = 0 v, v ref = 5 v, t a = ?0 to 85 ?, unless otherwise noted) unit parameter symbol limits typ. min. max. test conditions resolution absolute accuracy set time output resistance reference power source input current t su r o i vref (note) 1 2.5 8 ?1.0 3 4 3.2 bits % s k ? ma note: the test conditions are as follows: ?one d-a converter is used. ?the d-a register value of the unused d-a converter is ?0 16 . ?the reference power source input current for the ladder resistance of the a-d converter is excluded. s reset input low-level pulse width t w(resetl) symbol parameter min. limits unit reset input reset input timing requirements (v cc = 5 v ?0.5 v, v ss = 0v, ta = ?0 to 85 ?, unless otherwise noted) 2 max. typ. reset input t w(resetl)
117 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers t c(ta) t w(tah) t w(tal) f(f sys ) 26 mhz f(f sys ) 26 mhz f(f sys ) 26 mhz peripheral device input/output timing (v cc = 5 v?.5 v, v ss = 0 v, t a = ?0 to 85 ?, f(f sys ) = 26 mhz unless otherwise noted) ? for limits depending on f(f sys ), their calculation formulas are shown below. also, the values at f(f sys ) = 26 mhz are shown in ( ). timer a input (up-down input and count input in event counter mode) t c(up) t w(uph) t w(upl) t su(up-t in ) t h(t in -up) symbol tai out input cycle time tai out input high-level pulse width tai out input low-level pulse width tai out input setup time tai out input hold time parameter limits min. 2000 1000 1000 400 400 max. ns ns ns ns ns unit timer a input (external trigger input in pulse width modulation mode) t w(tah) t w(tal) symbol tai in input high-level pulse width tai in input low-level pulse width parameter min. 80 80 limits max. ns ns unit limits symbol parameter min. max. unit 8 10 9 f(f sys ) (307) tai in input cycle time tai in input high-level pulse width tai in input low-level pulse width ns ns ns 80 80 timer a input (external trigger input in one-shot pulse mode) limits symbol parameter min. max. unit 16 10 9 f(f sys ) 8 10 9 f(f sys ) 8 10 9 f(f sys ) (615) (307) (307) t c(ta) t w(tah) t w(tal) tai in input cycle time tai in input high-level pulse width tai in input low-level pulse width ns ns ns timer a input (gating input in timer mode) note : the tai in input cycle time requires 4 or more cycles of a count source. the tai in input high-level pulse width and the tai in input low-level pulse width respectively require 2 or more cycles of a count source. the limits in this table are applied when the count source = f 2 at f(f sys ) 26 mhz. timer a input (count input in event counter mode) t c(ta) t w(tah) t w(tal) symbol tai in input cycle time tai in input high-level pulse width tai in input low-level pulse width parameter min. 80 40 40 limits max. ns ns ns unit f(f sys ) 26 mhz
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 118 t c(ta) t su(ta jin -ta jout ) t su(ta jout -ta jin ) symbol parameter min. 800 200 200 limits max. ns ns ns unit timer a input (two-phase pulse input in event counter mode) tai in input cycle time taj in input setup time taj out input setup time tai in input tai out input (up-down input) tai out input (up-down input) tai in input (when count by falling) tai in input (when count by rising) taj in input taj out input test conditions ?v cc = 5 v 0.5 v, ta = ?0 to 85 c ?input timing voltage : v il = 0.8 v, v ih = 2.15 v ?up-down and count input in event counter mode ?two-phase pulse input in event counter mode ?gating input in timer mode ?count input in event counter mode ?external trigger input in one-shot pulse mode ?external trigger input in pulse width modulation mode tc (ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t h(t in -up) t su(taj in -taj out ) t su(taj in -taj out ) t su(taj out -taj in ) t su(taj out -taj in ) t c(ta) t su(up-t in )
119 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers f(f sys ) 26 mhz f(f sys ) 26 mhz f(f sys ) 26 mhz f(f sys ) 26 mhz f(f sys ) 26 mhz f(f sys ) 26 mhz t c(tb) t w(tbh) t w(tbl) t c(tb) t w(tbh) t w(tbl) timer b input (count input in event counter mode) symbol tbi in input cycle time (one edge count) tbi in input high-level pulse width (one edge count) tbi in input low-level pulse width (one edge count) tbi in input cycle time (both edge count) tbi in input high-level pulse width (both edge count) tbi in input low-level pulse width (both edge count) parameter limits min. 80 40 40 160 80 80 max. ns ns ns ns ns ns unit limits symbol parameter min. max. unit 16 10 9 f(f sys ) 8 10 9 f(f sys ) 8 10 9 f(f sys ) (615) (307) (307) t c(tb) t w(tbh) t w(tbl) tbi in input cycle time tbi in input high-level pulse width tbi in input low-level pulse width ns ns ns timer b input (pulse period measurement mode) note: the tbi in input cycle time requires 4 or more cycles of a count source. the tbi in input high-level pulse width and the tbi in input low-level pulse width respectively require 2 or more cycles of a count source. the limits in this table are applied when the count source = f 2 at f(f sys ) 26 mhz. limits symbol parameter min. max. unit 16 10 9 f(f sys ) 8 10 9 f(f sys ) 8 10 9 f(f sys ) (615) (307) (307) t c(tb) t w(tbh) t w(tbl) tbi in input cycle time tbi in input high-level pulse width tbi in input low-level pulse width ns ns ns timer b input (pulse width measurement mode) note: the tbi in input cycle time requires 4 or more cycles of a count source. the tbi in input high-level pulse width and the tbi in input low-level pulse width respectively require 2 or more cycles of a count source. the limits in this table are applied when the count source = f 2 at f(f sys ) 26 mhz. t c(ad) t w(adl) symbol ad trg input cycle time (minimum allowable trigger) ad trg input low-level pulse width parameter min. 1000 125 limits max. ns ns unit a-d trigger input
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 120 t c(ck) t w(ckh) t w(ckl) t d(c-q) t h(c-q) t su(d-c) t h(c-d) serial i/o symbol clk i input cycle time clk i input high-level pulse width clk i input low-level pulse width t x d i output delay time t x d i hold time r x d i input setup time r x d i input hold time parameter limits min. 200 100 100 0 20 90 max. 80 ns ns ns ns ns ns ns unit t w(inh) t w(inl) symbol int i input/nmi input/kii input high-level pulse width int i input/nmi input/kii input low-level pulse width parameter min. 250 250 limits max. ns ns unit external interrupt (int i ) input, nmi input, key input interrupt (kii) input t c(tb) t w(tbh) t w(tbl) t c(ck) t w(ckh) t w(ckl) t h(c - q) t d(c - q) t su(d - c) t w(inh) t w(inl) t h(c - d) t c(ad) t w(adl) tbi in input inti input, ad trg input clki input txdi output rxdi input nmi input, kii input test conditions vcc = 5 v 0.5 v, ta = 20 to 85 c input timing voltage : v il = 0.8 v, v ih = 2.15 v output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 50 pf
121 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers t d( 1-hldal) t d(rdh-hldal) t d(bxwh-hldal) t pxz(hldal-rdz) t pxz(hldal-bxwz) t pxz(hldal-csiz) t pxz(hldal-alez) t pxz(hldal-az) t pzx(hldal-rdz) t pzx(hldal-bxwz) t pzx(hldal-csiz) t pzx(hldal-alez) t pzx(hldal-az) ready, hold timing timing requirements (v cc = 5 v?.5 v, v ss = 0 v, t a = ?0 to 85 ?, f(f sys ) = 26 mhz, unless otherwise noted) t su(rdy- 1) t su(hold- 1) t h( 1-rdy) t h( 1-hold) symbol rdy input setup time hold input setup time rdy input hold time hold input hold time parameter limits min. 40 40 0 0 max. ns ns ns ns unit switching characteristics (v cc = 5 v?.5 v, v ss = 0 v, t a = ?0 to 85 ?, f(f sys ) = 26 mhz, unless otherwise noted) symbol hlda output delay time hlda low-level output delay time after read hlda low-level output delay time after write floating start delay time floating start delay time floating start delay time floating start delay time floating start delay time floating release delay time floating release delay time floating release delay time floating release delay time floating release delay time parameter min. tc ?5 (note) tc ?5 (note) ?5 ?5 ?5 ?5 ?5 0 0 0 0 0 limits max. 20 10 10 10 10 10 ns ns ns ns ns ns ns ns ns ns ns ns ns unit note: tc = 1/f(f sys ).
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 122 1 rdy input t su (rdy- 1 ) rd, blw, bhw : wait inserted by software (the above is applied when bus cycle = 1 + 2 ) : wait inserted by ready function rdy input t h ( 1 -rdy) test conditions v cc = 5 v 0.5 v, ta= 20 to 85 c rdy input, hold input : v il = 0.8v, v ih = 2.15 v hlda output : v ol = 0.8v, v oh = 2.0 v, c l = 50 pf 1 hold input t su (hold- 1) t d ( 1-hldal) t pxz (hldal-rdz) t pxz (hldal-bxwz) t pxz (hldal-csiz) t pxz (hldal-az) t h ( 1-hold) t d ( 1-hldal) t pzx (hldal-rdz) t pzx (hldal-bxwz) t pzx (hldal-csiz) t pzx (hldal-alez) t pzx (hldal-az) hi-z hi-z hi-z hi-z hi-z hold input hlda output rd blw bhw cs i a 0 a 23 output t d (rdh-hldal) t d (bxwh-hldal) t pxz (hldal-alez) ale
123 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers t c(in) t w(half) t w(h) t w(l) t r t f t a(a-d) t a(a-d) t a(csil-d) t a(rdl-d) t su(d-rdl) t h(rdh-d) t a(ba-d) t h(ba-d) t a(la-d) max. 0.55 tc (w h + w l ) tc-45 (w h + w l -0.5) tc-35 (w h + w l -0.5) tc-35 w l tc-30 w l tc-35 min. 38 0.45 tc 0.5 t c ?6 0.5 t c ?6 6 6 15 0 8 (w h + w l -0.5)tc-35 (note) external clock input cycle time external clock input pulse width with half input-volage external clock input high-level pulse width external clock input low-level pulse width external clock input rise time external clock input fall time address access time (the address output select bit = 0) address access time (the address output select bit = 1) chip select access time read access time read data setup time data input hold time after read address access time at burst rom access data hold time after address at burst rom access address access time (the multiplexed bus select bit = 1) 1 +1 1 +2 1 +3 2 +2 limits external bus timing for limits depending on f(f sys ), their calculation formulas are shown below. symbol parameter ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns unit external clock input t r t f t w(l) t w(h) t w(half) x in t c(in) test conditions vcc = 5 v 0.5 v, ta = 20 to 85 c input timing voltage : v il = 1.0 v, v ih = 4.0 v (t w(h) , t w(l) , t r , t f ) output timing voltage : 2.5 v ( t c(in) , t w(half) ) bus cycle w h w l 1 1 1 2 1 2 3 2 bus cycle w h w l 2 +3 2 +4 3 +3 3 +4 2 2 3 3 3 4 3 4 tc = 1/f(f sys ). timing requirements (v cc = 5 v?.5 v, v ss = 0 v, t a = ?0 to 85 ?, f(x in ) = 26 mhz, unless otherwise noted) note: this is independent of the address output select bits contents.
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 124 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns bus cycle = 2 + 2 bus cycle = 3 + 3 , 3 + 4 t d( 1-rdl) t d( 1-rdh) t d( 1-bxwl) t d( 1-bxwh) t d( 1l-csil) t d( 1l-csih) t d( 1h-a) t d( 1l-a) t w(aleh) t d(a-alel) t w(rdl) t w(rdh) t d(rdh-bxwh) t d(a-rdh) t d(a-rdh) t h(rdh-a) t h(rdh-a) t d(rdh-alel) t d(alel-rdh) t d(csil-rdh) t d(csil-rdl) t h(rdh-csil) t d(rdh-d) t w(bxwl) t w(bxwh) t d(bxwh-rdh) t d(a-bxwh) t d(a-bxwh) t h(bxwh-a) t h(bxwh-a) t d(bxwh-alel) t d(alel-bxwh) t d(csil-bxwh) t d(csil-bxwl) t h(bxwh-csil) t d(d-bxwl) t h(bxwh-d) t pxz(bxwh-dz) parameter switching characteristics (v cc = 5 v?.5 v, v ss = 0 v, t a = ?0 to 85 ?, f(f sys ) = 26 mhz, unless otherwise noted) max. 0 0 0 0 0 10 25 16 20 20 0.5tc + 10 min. ?8 ?8 ?8 ?8 ?0 ?2 ? ?0 0.5tc-19 tc-20 1.5tc-20 tc-30 1.5tc-30 2tc-30 0.5tc-19 tc-20 1.5tc-20 w l tc-15 w h tc-15 tc-15 w h tc-30 (w h -0.5)tc-19 8 0.5tc-10 0.5tc-19 tc-15 (w h -0.5)tc-19 (w h + w l -0.5)tc-20 0.5tc-14 tc-15 w l tc-15 w h tc-15 tc-15 w h tc-30 (w h -0.5)tc-19 8 0.5tc-10 0.5tc-19 tc-15 (w h -0.5)tc-19 (w h + w l -0.5)tc-20 0.5tc-14 w l tc-20 0.5tc-10 read low-level output delay time read high-level output delay time write low-level output delay time write high-level output delay time chip select low-level output delay time chip select high-level output delay time address output delay time (the address output select bit = 0) address output delay time (the address output select bit = 1) ale pulse width ale completion delay time after address stabilization (when the address output select bit = 0) ale completion delay time after address stabilization (when the address output select bit = 1) read output pulse width read output high-level width (note 1) write disable valid time after read (note 2) address valid time before read (when the address output select bit = 0) address valid time before read (when the address output select bit = 1) address hold time after read (when the address output select bit = 0) (note 2) address hold time after read (when the address output select bit = 1) (note 2) ale completion delay time after read start read disable valid time after ale completion chip select valid time before read chip select output valid time before read completion chip select hold time after read next write cycle data output delay time after read (note 2) write output pulse width write output high-level width (note 1) read disable valid time after write (note 2) address valid time before write (when the address output select bit = 0) address valid time before write (when the address output select bit = 1) address hold time after write (when the address output select bit = 0) (note 2) address hold time after write (when the address output select bit = 1) (note 2) ale completion delay time after write start write disable valid time after ale completion chip select valid time before write chip select output valid time before write completion chip select hold time after write data output valid time before write completion data hold time after write (note 3) floating start delay time after write (note 3) limits symbol unit bus cycle = 1 + 1 , 1 + 2 , 1 + 3 bus cycle = 2 + 2 bus cycle = 2 + 3 , 2 + 4 , 3 + 3 , 3 + 4 bus cycle = 1 + 1 , 1 + 2 , 1 + 3 bus cycle = 2 + 2 bus cycle = 2 + 3 , 2 + 4 , 3 + 3 , 3 + 4 bus cycle = 2 + 2 bus cycle = 2 + 3 , 2 + 4 , 3 + 3 , 3 + 4 notes 1: when the bus cycle just before this parameter is for the area where the recovery cycle insertion is selected, this parameter is extended by tc (ns: one recovery cycle is inserted.) or by 2tc (ns: two recovery cycles are inserted.). 2: when accessing the area where the recovery cycle insertion is selected, this parameter is extended by tc (ns: one recovery cycl e is inserted.) or by 2tc (ns: two recovery cycles are inserted.). 3: this parameter is extended by tc (ns) when both of the following conditions are satisfied: ?when accessing the area where the recovery cycle insertion is selected. ?when two recovery cycles are inserted. bus cycle = 1 + 1 , 1 + 2 , 1 + 3 bus cycle = 2 + 2 bus cycle = 2 + 3 , 2 + 4 , 3 + 3 , 3 + 4
125 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers t d(la-rdh) t d(la-alel) t h(alel-la) t pxz(rdh-laz) t d(la-bxwh) t pzx(rdh-dz) address valid time before read ale completion delay time after address stabilization address hold time after ale completion floating start delay time address valid time before write floating release delay time bus cycle = 2 + 2 bus cycle = 3 + 3 , 3 + 4 bus cycle = 2 + 2 bus cycle = 3 + 3 , 3 + 4 switching characteristics (v cc = 5 v?.5 v, v ss = 0 v, t a = ?0 to 85 ?, f(f sys ) = 26 mhz, unless otherwise noted) parameter max. 5 min. (w h -0.5)tc-19 (note) tc-20 (note) 1.5tc-20 (note) 0.5tc-19 tc-15 (w h -0.5)tc-19 (note) 0.5tc-19 (note) limits symbol ns ns ns ns ns ns ns ns unit note: this is independent of the address output select bits contents.
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 126 bus cycle t h(rdh-d) t h(rdh-a) t w(rdl) t a(csil-d) t a(rdl-d) t a(a-d) t d(csil-rdl) t su(d-rdl) t w(aleh) t d(rdh-alel) t c t d(a-alel) t w(rdh) t d(rdh-d) t d( 1-rdl) t h(rdh-a) t d(a-rdh) t d(csil-rdh) t a(a-d) t d(a-alel) t d( 1h-a) t d( 1l-a) t d( 1l-csil) t d( 1l-csih) t d( 1-rdh) t h(rdh-csil) t d(rdh-bxwh) t d(a-rdh) cs i rd ale 1 f sys blw bhw normal access: bus cycle = 1 + 1 , 1 + 2 , 1 + 3 , 2 + 3 , or 2 + 4 a 0 a 23 (when the address output select bit = 0) a 0 a 23 (when the address output select bit = 1) d 0 d 7 , d 8 d 15 test conditions v cc = 5 v 0.5 v, ta = 20 to 85 c input timing voltage : v il =0.8 v, v ih =2.15 v output timing voltage: v ol =0.8 v, v oh =2.0 v, c l =15 pf (cs i ) output timing voltage: v ol =0.8 v, v oh =2.0 v, c l =50 pf (except for cs i )
127 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers t h(bxwh-a) t d(csil-bxwl) t w(bxwl) t d(bxwh-alel) t d(d-bxwl) t h(bxwh-d) t pxz(bxwh-dz) bus cycle t d( 1-bxwl) t h(bxwh-a) t d(a-bxwh) t d(csil-bxwh) t c t d(a-alel) t w(aleh) t d( 1h-a) t d( 1l-csil) t d( 1l-csih) t d(bxwh-rdh) t d( 1-bxwh) t h(bxwh-csil) t d(a-alel) t w(bxwh) t d(a-bxwh) t d( 1l-a) cs i rd ale blw bhw 1 f sys normal access: bus cycle = 1 + 1 , 1 + 2 , 1 + 3 , 2 + 3 , or 2 + 4 a 0 ? 23 (when the address output select bit = 0) a 0 ? 23 (when the address output select bit = 1) d 0 ? 7 , d 8 ? 15 test conditions ?v cc = 5 v 0.5 v, ta = ?0 to 85 c ?input timing voltage : v il =0.8 v, v ih =2.15 v ?output timing voltage: v ol =0.8 v, v oh =2.0 v, c l =15 pf (cs i ) ?output timing voltage: v ol =0.8 v, v oh =2.0 v, c l =50 pf (except for cs i )
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 128 t d(a-rdh) bus cycle t d(csil-rdl) t d(a-alel) t h(rdh-d) t h(rdh-a) t w(rdl) t a(csil-d) t a(rdl-d) t a(a-d) t su(d-rdl) t w(aleh) t c t w(rdh) t d(rdh-d) t d(alel-rdh) t d( 1-rdl) t d( 1-rdh) t h(rdh-d) t a(la-d) t a(rdl-d) t d(la-rdh) t su(d-rdl) t pzx(rdh-dz) t d(la-alel) t h(alel-la) t pxz(rdh-laz) t h(rdh-a) t d(a-rdh) t d(csil-rdh) t a(a-d) address input data address t d( 1h-a) t d( 1l-csil) t d( 1l-csih) t d(rdh-bxwh) t h(rdh-csil) t d(a-alel) t d( 1l-a) cs i rd ale blw bhw f sys 1 note: valid only when area cs 2 is accessed with the external data bus width = 8 bits. normal access: bus cycle = 2 + 2 , 3 + 3 , 3 + 4 a 0 a 23 (when the address output select bit = 0) d 0 d 7 , d 8 d 15 (when the multiplexed bus select bit = 0) la 0 /d 0 la 7 /d 7 (when the multiplexed bus select bit = 1, note ) a 0 a 23 (when the address output select bit = 1) test conditions v cc = 5 v 0.5 v, ta = 20 to 85 c input timing voltage : v il =0.8 v, v ih =2.15 v output timing voltage: v ol =0.8 v, v oh =2.0 v, c l =15 pf (cs i ) output timing voltage: v ol =0.8 v, v oh =2.0 v, c l =50 pf (except for cs i )
129 m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers t d(csil-bxwl) t h(bxwh-a) t d(a-bxwh) t w(aleh) t w(bxwl) t d(d-bxwl) t h(bxwh-d) t pxz(bxwh-dz) t d(a-alel) t w(bxwh) t d(alel-bxwh) bus cycle t d( 1-bxwl) t h(bxwh-d) t pxz(bxwh-dz) t d(d-bxwl) t h(alel-la) t d(la-alel) t d(la-bxwh) t c t h(bxwh-a) t d(a-bxwh) t d(csil-bxwh) address output data t d( 1-bxwh) t d( 1h-a) t d( 1l-csil) t d( 1l-csih) t d(a-alel) t h(bxwh-csil) t d(bxwh-rdh) t d( 1l-a) cs i rd ale blw bhw f sys 1 note: valid only when area cs 2 is accessed with the external data bus width = 8 bits. normal access: bus cycle = 2 + 2 , 3 + 3 , 3 + 4 a 0 ? 23 (when the address output select bit = 0) d 0 ? 7 , d 8 ? 15 (when the multiplexed bus select bit = 0) la 0 /d 0 ?a 7 /d 7 (when the multiplexed bus select bit = 1, note ) a 0 ? 23 (when the address output select bit = 1) test conditions ?v cc = 5 v 0.5 v, ta = ?0 to 85 c ?input timing voltage : v il =0.8 v, v ih =2.15 v ?output timing voltage: v ol =0.8 v, v oh =2.0 v, c l =15 pf (cs i ) ?output timing voltage: v ol =0.8 v, v oh =2.0 v, c l =50 pf (except for cs i )
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers 130 t h(ba-d) t d(rdh-bxwh) blw bhw rd t a(rdl-d) t d(a-rdh) cs i t h(rdh-a) t a(csil-d) t a(a-d) t a(ba-d) t h(ba-d) t h(ba-d) t h(rdh-d) t a(ba-d) t a(ba-d) t h(rdh-csil) t d(csil-rdh) t d(a-alel) t w(aleh) ale t d(rdh-alel) t w(rdh) t d(a-rdh) t h(rdh-a) t a(a-d) burst rom access: bus cycle = 1 + 1 , 1 + 2 , 1 + 3 , 2 + 3 , 2 + 4 d 0 d 7 , d 8 d 15 test conditions v cc = 5 v 0.5 v, ta = 20 to 85 c input timing voltage : v il =0.8 v, v ih =2.15 v output timing voltage: v ol =0.8 v, v oh =2.0 v, c l =15 pf (cs i ) output timing voltage: v ol =0.8 v, v oh =2.0 v, c l =50 pf (except for cs i ) a 0 a 23 (when the address output select bit = 0) a 0 a 23 (when the address output select bit = 1) t d(a-alel)
m37902fcchp, m37902fgchp, m37902fjchp single-chip 16-bit cmos microcomputer mitsubishi microcomputers notes regarding these materials these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product be st suited to the customer s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-party s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents info rmation on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommen ded that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assu mes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubish i semiconductor home page (http://www.mitsubishichips.com). when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibilit y for any damage, liability or other loss resulting from the information contained herein. mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used unde r circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a pro duct contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these ma terials. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a licens e from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further detail s on these materials or the products contained therein. ? 2000 mitsubishi electric corp. new publication, effective jun., 2000. specifications subject to change without notice. keep safety first in your circuit designs! mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making y our circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. package outline lqfp100-p-1414-0.50 weight(g) jedec code eiaj package code lead material cu alloy 100p6q-a plastic 100pin 14 ? 0.1 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.225 i 2 1.0 m d 14.4 m e 14.4 10 0 0.1 1.0 0.7 0.5 0.3 16.2 16.0 15.8 16.2 16.0 15.8 0.5 14.1 14.0 13.9 14.1 14.0 13.9 0.175 0.125 0.105 0.28 0.18 0.13 1.4 0 1.7 e e e e c h e 1 76 75 51 50 26 25 h d d m d m e a f b a 1 a 2 l 1 l y b 2 i 2 recommended mount pad detail f 100
rev. rev. no. date 1.0 first edition 990305 2.0 refer to corrections and supplementary explanation for ?37902fxc datasheet (rev.a)? 990625 3.0 the following are revised/added points in this edition: 990917 ?figure 26 in page 40; the bit? name (bit 7) of the port function control register pin nmi pullup connection select bit (note 2) pin nmi pullup select bit (note 2) ?page 95; clock generating circuit , right column, line 10 ?the pll output clock (f pll ). (in other words, set bit 5 to ??) ? the pll output clock (f pll ). (in other words, set bit 5 to ??) note that, after reset, the pll multiplication ratio select bits are allowed to be changed only once. ?table 15 in page 95; note is revised. ?f(x in ) means the frequency of the input clock from pin x in f(x in ). ?f(x in ) means the frequency of the input clock from pin x in f(x in ). after reset, the pll multiplication ratio select bits are allowed to be changed only once. ?page 120; recommended operating conditions f(f sys ) external clock input frequency (note 2) f(x in ) external clock input frequency (note 2) 4.0 the following are revised/added points in this edition: 991008 ?page 83; d-a converter , left column, line 15 t he d-a output enable bit is cleared to ??at reset. the contents of the corresponding d-a output enable bit and d-a register are cleared to ??at reset. ?page 83; d-a converter , right column, line 1 with pin d-ai. with pin d-ai. also, when not using the d-a converter, be sure to clear the contents of the corresponding d-a output enable bit and d-a register to ?? 5.0 refer to corrections and supplementary explanation for ?37902fxc datasheet (rev.b)? 000629 notes 1: represents the new information added in rev.5.0. 2: the revised/added points informed in rev.3.0 and rev.4.0 are included in corre- ctions and supplementary explanation for ?37902fxc datasheet (rev.b)? revision history m37902fxchp datasheet (1/1) revision description
corrections and supplement ar y explanation for m37902fxc dat asheet (rev. b) no.1 page erro r correction (1/11) page 3 , b lo c k diagra m , no t e : note: ram 2048 bytes 4096 bytes 6144 bytes 6144 bytes 12288 bytes 12288 bytes m37902f8 c g p ,m37902f8 c h p m37902fc cgp ,m3790 2f c chp m37902fecgp,m37902fechp M37902FGCGP, m 37902fg c hp m37902fh cgp ,m3790 2f h chp m37902fjc g p,m37902fjch p flash memory 60 kbytes 120 kbytes 184 kbytes 248 kbytes 370 kbytes 498 kbytes note: ram 4096 bytes 6144 bytes 12288 bytes m37902f c c h p m37902fgch p m37902fjc hp flash memory 120 kbytes 248 kbytes 498 kbytes all pages, h eade r preliminary notice: this is not a final specification. some parametric limits are subject to change. (deleted) p6 3 / int 2 p6 4 /int 2 page 2 , pin confi gur at io n page 105 , fig . 112 , pi n conne ct i on o f m3790 2f xc hp i n f l ash m emor y m37902f8 c g p , m37902f 8 c hp , m37902f c cg p, m37902fc chp , m37902fe cgp, m 37902 fec hp, M37902FGCGP, m37902fgchp , m37902f hcgp, m37902fh chp , m37902fjc g p , m37902fjc hp m37902f c c hp , m37902f gc h p, m37902f j c hp page 1, disti n cti ve feat u res ; m emory [m 379 02f8 cg p , m37902f8 c hp] fl ash memor y (user r o m ar ea ) .. .... .... ... .... .... .60 kbytes ra m ... .... .... .... ... .... .... .... ... .... .... .... .... ... .... .... .... .2048 bytes (deleted) [m 379 02f cc g p , m37902f c c hp ] fl ash memor y (user r o m ar ea ) .. .... .... ... .... ...120 kbytes ra m ... .... .... .... ... .... .... .... ... .... .... .... .... ... .... .... .... .4096 bytes [m 379 02f cc hp] fl ash memor y (user r o m ar ea ) .. .... .... ... .... ...120 kbytes ra m ... .... .... .... ... .... .... .... ... .... .... .... .... ... .... .... .... .4096 bytes [m37902fe cg p, m37902fe c hp] flash memory (user rom area) ....................184 kbytes ram.................................................................6144 bytes (deleted) [m37902f gcg p, m37902f gc hp] flash memory (user rom area) ....................248 kbytes ram.................................................................6144 bytes [m37902f gc hp] flash memory (user rom area) ....................248 kbytes ram.................................................................6144 bytes [m37902fh cg p, m37902fh c hp] flash memory (user rom area) ....................370 kbytes ram...............................................................12288 bytes (deleted) [m 379 02fj cg p, m37902fj c h p] fl ash memor y (user r o m ar ea ) .. .... .... ... .... ...498 kbytes ra m ... .... .... .... ... .... .... .... ... .... .... .... .... ... .... .... ...12288 byt e s [m 379 02fj c h p] fl ash memor y (user r o m ar ea ) .. .... .... ... .... ...498 kbytes ra m ... .... .... .... ... .... .... .... ... .... .... .... .... ... .... .... ...12288 byt e s page 1, appli c at ion c ontrol devices for personal computer peripheral equi p- ment such as cd-rom drives, dv d- r o m dr i ves, hard disk drives, high density fdd , printers control devices for office equipment such as copi er s and f a csim i les control devices for in dust rial eq uipment such as comm u- nication and measuring instrum ents c ontrol devices for personal computer peripheral equip- ment such as cd-rom drives, dvd-rom drives, hard disk drives, high density fdd, printers m37902fx c g p p in c onfi g ura tio n (top v i e w) (deleted) m37902f8 c hp m37902fcchp m37902fechp m37902fgchp m37902fhchp m37902fjchp m37902f cc hp m37902fgchp m37902fjchp (type) (type) pa ge 4, ch ip-selec t wait control c hi p sel ect area ? 4 ( c s 0 c s 3 ) . a wai t number an d bus width can be set for each ch ip select ar ea. c hi p sel ect area ? 4 ( c s 0 c s 3 ) . a bus cycle type and bus width can be set for e ach ch ip select a r ea.
corrections and supplement ar y explanation for m37902fxc dat asheet (rev. b) no.2 page erro r correction (2/11) 00ffc0 16 internal f l ash memory 120 kbytes (user rom area) 00 ffff 16 002000 16 00ffc0 16 internal f l ash memory 120 kbytes (user rom area) 00ffff 16 002000 16 page 9, memory, line 2 . the addre ss spa ce i s 1 6 mb yt es from address 0 16 to ffff ff 16 . . the address space is 16 mbytes from addresses 0 16 to ffffff 16 . page 4, paramete r pa ge 6, p4 0 ?4 7 i n mi croprocessor mode . according to the register setting, p4 0 ?4 4 also i n mi croprocessor mode . according to the register setting, p4 0 ?4 3 also operating temperature range oper a t i ng a m bie nt tem p er ature r ange page 4 , no t e : note: ram 2048 bytes 4096 bytes 6144 bytes 6144 bytes 12288 bytes 12288 bytes m37902f8 c g p ,m37902f8 c h p m37902fc cgp ,m3790 2f c chp m37902fecgp,m37902fechp M37902FGCGP, m 37902fg c hp m37902fh cgp ,m3790 2f h chp m37902fjc g p,m37902fjch p flash memory (user rom area) 60 kbytes 120 kbytes 184 kbytes 248 kbytes 370 kbytes 498 kbytes m37902f8 c g p ,m37902f8 c h p m37902fc cgp ,m3790 2f c chp m37902fecgp,m37902fechp M37902FGCGP, m 37902fg c hp m37902fh cgp ,m3790 2f h chp m37902fjc g p,m37902fjch p note: ram 4096 bytes 6144 bytes 12288 bytes m37902f cc h p m37902fgchp m37902fjchp flash memory (user rom area) 120 kbytes 248 kbytes 498 kbytes m37902f cc h p m37902fgchp m37902fjchp page 5, notes 1: user r o m area m37902f8c g p, m 37902f8ch p 4 bl ocks m37902fccgp, m37902fcchp 5 blocks m37902fecgp, m37 902fe c hp 6 bl ocks M37902FGCGP, m37902 f gch p 7 bl ocks m37902fhcgp, m37902fhchp 9 blocks m37902fjc g p, m 37902fjchp 11 bl ocks user r o m area m37902fc chp 5 blocks m37902fgchp 7 blocks m37902fjchp 11 blocks page 9, fig. 1 fi g. 2. m emory map of m37902f ccg p and m37902fc chp (si ngle-chip m od e) fig. 1. memory map of m37902f cc hp (single-chip mode) memory map of m37902f8 cg p and m37902f8 c hp (single-chip mode) (deleted) mem ory m ap of m 379 02fe c g p and m 37902 fe c hp (singl e- chi p m ode) (deleted) mem ory m ap of m 379 02fh c g p an d m37902f h c hp (singl e- chi p m ode) (deleted)
corrections and supplement ar y explanation for m37902fxc dat asheet (rev. b) no.3 page erro r correction (3/11) 00ff c0 16 internal f l ash memory 248 kbytes (user rom area) 00 ffff 16 003800 16 00ffc0 16 internal f l ash memory 248 kbytes (user rom area) 00ffff 16 003800 16 00ff c0 16 internal f l ash memory 498 kbytes (user rom area) 00ffff 16 003800 16 00ffc0 16 internal f l ash memory 498 kbytes (user rom area) 00ffff 16 003800 16 po r t 011 direct i on re g i st er 000019 16 00001a 16 port p11 direction re g ister 000019 16 00001a 16 page 11, fig. 7 000000 16 000001 16 000000 16 000001 16 reserved area (note) reserved area (note) address 00 16 , 01 16 address 19 16 fi g. 4. m emory map of m37902f g c g p and m37902fgch p ( s ingle-chip mode) fig. 2. memory map of m37902f gc hp (single-chip mode) page 10, fig. 2 fi g. 6. m emory map of m37902f j cg p and m37902fjc hp (singl e- chi p mode) fig. 3. memory map of m37902fj c hp (single-chip mode) page 10, fig. 3 page 12, fig. 8 serial i/o control r e g i st e r 0 000ac 16 0 000ad 16 serial i/o p in control re g ister 0 000ac 16 0 000ad 16 address a6 16 address ac 16 , ad 16 reserved a r ea ( note ) 0000a 6 16 0000a 7 16 ( deleted )
corrections and supplement ar y explanation for m37902fxc dat asheet (rev. b) no.4 page erro r correction (4/11) b31 b0 db data bu ff er b31 b0 d q data bu ff er page 18, fig. 11 page 26, fig. 18, notes 1 n o t e s 1 : the number of bus cycles is determi- ned by the follow ing bits: notes 1: the bus cycle type is determined by the following bits: page 31, r ight column line 5 . therefore, ports p0 or p 4 , p10, p11 fun- ction as i/o pin s for the address bus, . therefore, ports p0 to p4, p10, p11 fun- ction as i/o pins for the address bus, mode (note 1) p in md0 p rocessor mode (note 2) page 33, table 5 mode (note 1) p in md0 p rocessor mode bi t s (note 2) page 35, fig. 24, note n o t e s 1 : w h i l e v s s , bit 1 is cleared to ?? while v c c ? bit 1 i s se t to ??at reset. (fixed to ??) notes 1: while v ss ? this bit? state is cleared to ??at reset. while v cc ? this bit? state is set to ??at reset. (fixed to ??) 3: while v ss ? bit 7 is cleared to ?? while v cc ? bit 7 is set to ??at reset. 3: while v ss ? this bit? state is cleared to ??at reset. while v cc ? this bit? state is set to ??at reset. w h i l e v s s ? these bits ar e cleared to ?? whil e v c c ? on the ot h er hand, t h ese b its are set to 1 . 4: while v ss ? each of these bits is ? at reset. while v cc ? on the other hand, each of these bits is 1? at reset. data buff e r temporari t y stores data which has bee n ? and external are as b y the biu or which is to be writeen to internal me mory, . temporarily stores data which has been , and external areas by the biu; or temporarily stores data which is to be written to internal memory, . page 18, table 1 i nstructio n queue buff e r temporarity stores an instruction which . temporarily stores an instruction which . p rocessor mode regi st er 1 10 2 43 5 6 7 recove ry-cycle-i nsert sel ect bi t int er nal r o m b us cycl e sel ect bit (note 6) page 36, fig. 25 p rocessor mode regi st er 1 10 2 43 5 6 7 recove ry-cycle-i nsert sel ect bi t (n o te 6) int er nal r o m b us cycl e sel ect bit (note 7) 2: a ft er r eset, t hi s b it? cont en t s can be switched only once. during the software execution, be su r e not t o swi t ch this bit? contents. 2: a ft er r eset, t hi s b it can be set only once. d ur i ng t he softwar e execu t i on, be sure not to change this bit. 5: in the memory expansion or microprocessor mode, if this bit? contents is switched from ??to ?, this bit will be cleared to ?. after this clearance, this bit cannot return to ?. if it is necessary to set this bit to ?, be sure to reset the microcomputer. 5: a ft er r eset, t he se bi t s can be set to ? only once. once t he se bi t s have been clea r ed to 0?f rom ?? they cannot be set to ?? ag ain. (fi xed t o ? .)
corrections and supplement ar y explanation for m37902fxc dat asheet (rev. b) no.5 page erro r correction (5/11) page 3 7 , fig. 26, bit 4 4 p ins p 4 4 p 4 7 pullup connectio n sel ect bit p ins p 4 4 p 4 7 pullup sel ect bit 4 7 p in nmi pull up conn ect i on sel ect bi t (n o te 2) 7 p in nmi pull up sel ect bi t (note 2) page 39, table 7 a r ea m ultiplexe d bus address (note 3) area multiplexed bus access (note 3) page 40, fig. 28, cs 0 control register l; note while v ss ? this bit is cleared to ?? while v cc ? this bit is set to ??at reset. notes 1: while v ss ? this bit? state is cleared to ??at reset. while v cc ? this bit? state is set to ??at reset. 5: while v ss ? this bit is cleared to ?? while v cc ? this bit is set to ??at reset. (fixed to ??) 5: while v ss ? this bit? state is cleared to ??at reset. while v cc ? this bit? state is set to ??at reset. (fixed to ??) 7: in the microprocessor mode, this bit is invalid. when the internal flash memory is reprogrammed in the cpu reprogramming mode, be sure to clear this bit to ?? 6: the program which switches this bit? contents must be assigned to the internal area. page 36, fig. 25 in the m icroprocessor mode, t hi s b it i s i nvalid. page 42, fig. 30, area csx star t address register (x = 0 to 3) page 43, fig. 31 256 k bytes 1fff ff 16 fffff 16 s tart address : 4000 16 1fff ff 16 fffff 16 s tart address : 4000 16 area c sx start address register (x = 0 to 2) 0 1 0 1 when mode 0 is area c sx start address register (x = 0 to 2) when mode 0 is ? at read. 2 2 area c s 3 start address register 0 1 0 1 these bi t s determ i ne area c s 3 start address register ? at read. 2 2 these bits determine
corrections and supplement ar y explanation for m37902fxc dat asheet (rev. b) no.6 page erro r correction (6/11) page 44, fig. 3 2 f0 000 16 (fff ff 16 ) 0 16 8000 16 block size : 4 kbytes e0000 16 (fffff 16 ) 0 16 8000 16 block size : 8 kbytes addresses w hich can be ( a ddr ess fff ff 16 is not i nclud ed; note 1 ) addresses w hich can be ( a ddr ess fff ff 16 is not i nclud ed; note 1 ) f0 00 16 ( f fff 16 ) 0 16 8000 16 block size : 4 kbytes e000 16 (ffff 16 ) 0 16 8000 16 block size : 8 kbytes addresses w hich can be (address ffff 16 i s not i nclud ed; note 1 ) addresses w hich can be (address ffff 16 i s not i nclud ed; note 1 ) page 45, fig. 3 3 bl ock si ze : 8 mbyt es addresses w hich can be (addresses 0 16 and ff0000 1 6 are not in cluded; n ote 1 ) 0 16 bl ock si ze : 8 mbyt es addresses which can be (addresses 0 16 and ff0000 16 to ffffff 16 are not included; note 1 ) 0 16 page 45, fig. 33, titl e fig. 33 area c s 0 / c s 1 / c s 2 (mode 1) and area c s 3 fig. 33 area c s 0 / c s 1 / c s 2 (mode 0) and area c s 3 page 46, left column, line 2 tabl e 8 sho ws t he interr u pt types and t h e table 8 shows the interrupt sources and the page 46, table 8, titl e tabl e 8. inter rupt t ypes and the interr upt vector add r esses tabl e 8. inter rupt sour ces and interr up t vector add r esses page 52, left column, line 5 to use these pins as timer input pins, the data direction register to use these pins as timer input pins, the port direction register page 55, fig. 46, bit 4 4 0 : increment o r decr ement accor ding t o up/down flag 1 : 4 0 : increment o r decr ement accor ding t o up/down bi t 1 : page 62, (2) e vent cou nt er m od e [01] part i cular function sel ect register 1 (bit 7 at address 63 16 ) part i cular function sel ect register 1 (bit 6 at address 63 16 ) page 64, fig. 6 4 1/16 d ivi d e r 1/2 di vi d e r c l ock synch ronous c l ock synch ronous (external cl ock) cl ock synchronous (exte rnal cl ock) transmit control circui t uar t 1/16 divider 1/2 divider c lock synchronous c lock synchronous (internal clock) cl ock synchronous (exte rnal cl ock) transmit control circui t uart page 59, left column, lines 14, 17, 2 2 ? timer a i st a r t bit ? coun t star t bit (li ne 15) (li ne 15)
corrections and supplement ar y explanation for m37902fxc dat asheet (rev. b) no.7 page erro r correction (7/11) page 64, fig. 65, bits 2 to 0, bi t 5, bit 6 s erial i/ o mode select bits 0 0 0 : serial i/o mode is invalid. 0 0 1 : 210 5 6 even/ o dd pari t y select bit 0 : p arity enable sele ct bit 0 : s erial i/ o mode select bits 0 0 0 : serial i/o is invalid. 0 0 1 : 210 5 6 o dd/even parity select bit 0: p arity enable bit 0: page 66, fig. 68, ua rt0/1 tr an sm it/r e ceive co nt rol register 0, bit 6 6 c lk polar ity sel ect bit 0 : at the f al ling , receive data i s i nput. cpl 6 c lk polarity select bit 0 : at the falling , receive data is input. when not in transfer, pin clk? level is ?? cpl page 68, left column, last l in e read out the rts k output turns back to l? read out the rts k output turns back to l? page 70, fig. 71 c lk porarity se lect bi t = 1 c lk porarity select bit = 0 c lk porarity se lect bi t = 0 c lk porarity select bit = 1 page 74, table 1 3 p in p 8 0 / c t s 0 /rt s 0 (note 1) functions c t s 2 p in p 8 1 / p 8 1 or c lk 0 p in p 8 0 / c t s 0 /rt s 0 (note 1) functions c t s 0 p in p 8 1 / p 8 1 or c lk 0 page 77, left column, line 1 2 ad t rg inp ut changes from ? to l?( or l?t o ?? ) ad t rg inp ut changes from ? to l?( or l?t o ?? ) page 77, l e f t column, line 1 4 ad t rg pin i s multipl exed with an a nalog voltage ad t rg pin i s multipl exed with an a nalog voltage page 76, fig. 7 7 ladder n et w or k resistor ladder network page 77, r i g h t column, lines 5 to 6 the ladder network or not the r esi st o r ladder network or not page 77, r i g h t column, line 1 0 the ladder net w or k can be cut off by disconnecting ladd er network the r esi st or ladder net w or k can be cut o f f by disconnect- ing resistor la dder network page 80, l e f t column, line 1 0 , the cor respondin g pi n ( da 0 t o da 2 ) outputs , the cor respondin g pi n ( d-a 0 to d-a 2 ) ou t puts
corrections and supplement ar y explanation for m37902fxc dat asheet (rev. b) no.8 page erro r correction (8/11) page 81, fig. 83, bits 1 and 0 1 wave f orm out p ut select bits 11 : rtp1 and rtp0 sel ect e d whe n pul se m ode 0 i s sel ect ed: r tp 1 and rtp1 page 86, fig. 91, bi t s 2 to 0 address/ p ort switch select bits 0 0 0 : 210 0 1 wave f orm out p ut select bits 11 : rtp1 and rtp0 sel ect e d whe n pul se m ode 0 i s sel ect ed: r tp 1 and rtp0 0 address/ p ort sw itch bi t s 0 0 0 : 210 page 80, l e f t column, line 1 5 the d-a output enable bit is cleared to ?? at reset . the contents of the corr espond ing d-a output enab le bit and d-a register are cleared t o ? at r eset. page 80, r i g h t column, line 1 wi t h pin d-ai .wi t h pin d-ai . al so, wh en n ot using the d-a convert e r , be sur e to clear the content s of t he corresponding d-a output enable bit and d-a register to 0? [i n side dott ed-li ne n ot incl uded] p4 0 / a le, p4 1 / 1 , p4 2 /hlda , page 87, fig. 89, 2nd diagram [i n side dott ed-li ne n ot incl uded] p4 0 / a le, p4 1 / 1 , p4 2 /hlda , p ort l at ch o utput p ort latch o ut put (int ern al peripher al devices) page 88, fig. 90, 3rd di agra m [inside dotted-line not included] p7 7 /an 7 /ad trg /da 1 /(int 2 ) [inside dotted-line included] p7 7 /an 7 /ad trg /da 1 /(int 2 ) page 82, right column, lines 1 to 3 when the waveform output select bits are set to ?1?(bit 1 = bit 0 = 1?, rtp1 3 to rtp1 0 and rtp0 3 to rtp0 0 become pulse output port pins. when the waveform output when the waveform output select bits are set to ?1?(bit 1 = bit 0 = 1?, pulse output port pins are divided into two groups; one consists of rtp1 3 to rtp1 0 , rtp0 3 , rtp0 2 and the other consists of rtp0 1 and rtp0 0 . when the waveform output page 90, fig. 92, address 70 16 0 00 ? a-d interrup t control register (70 16 ) 000 ? a-d conversion interr u pt cont rol register ( 7 0 16 ) page 89, fig. 93, address 81 16 000 0 cs 0 control regi st er h (81 16 ) 0 000 0 cs 0 control regi st er h (81 16 ) 1 page 91, left column, line 17 from pin x in and output a m ultip lied clock. from pin x in and generates a multiplied clock. page 91, left column, lines 11, 12 , the oscillatio n ci r cui t stops it? o p e r a t i o n a n d r e s u - m e s t h e c u r r e n t d i s s i p a t i o n . , the oscillatio n ci r cui t stops it? o p e r a t i o n , a n d t h e c u r r e n t d i s s i p a t i o n i s r e d u c e d . page 92, right column, lines 4 to 5 in t h is selection, be su r e that multipl ied f (x i n ) does not exceed 26 m hz. t he p ll m ul t i plication ratio m ust be set so that the fr equ ency o f the pll output cl ock ( f pll ) must be in the range f rom 10 mhz to 26 mhz. page 92, right column, lines 10 to 11 ? the pll output clock ( f pl l ) . ( in other words, set bit 5 to 1?) ? the pll output clock ( f pl l ) . ( in other words, set bit 5 to 1?) note t h at , aft er r ese t , t h e p ll m ul t i plication ratio select bits ar e al lowed to be ch anged only once.
corrections and supplement ar y explanation for m37902fxc dat asheet (rev. b) no.9 page erro r correction (9/11) page 92, table 15, not e no t e: be sur e that syst em clock f sys doe s not exceed 26 mhz. f (x i n ) m ean s the fr eque ncy of the input clock fr om pin x i n (f x in ) . no t e: the pll multipli cat i on r atio must be set so that the frequency of the pll output clock ( f pll ) must be i n the range f rom 10 mhz to 26 mhz. f (x i n ) m eans the frequency of the input clock fr om pin x i n (f x in ) . after reset, the pll multipli cation r atio sel ect bits are al lowed to be changed only once. page 98, right column, line 8 page 98, right column, line 1 0 the ladder net w or k of t he a - d converter wi ll the resistor ladder network of the a-d converter will pin v ref to the ladder network, and the power dissipation pin v ref to the resistor ladder network, and the power dissipation page 96, left column, line 7 ? the oscil lation circuit a nd p ll circuit ha ve be en rest arted ? the oscil lation circuit h as be en restar ted m37902f8 c g p , m37902f 8 c hp : block configuration of internal flash m emory (deleted) fi g. 106. m 3 7902fj cg p , m37902fj c hp : b lock confi- guration of i nt ernal flash mem ory fig. 106. m37902fj c hp : block configuration of inter- nal flash memory page 101, fig. 10 6 fi g. 108. m 3 7902f cc g p , m37902f cc hp : block con- figuration of i nt ernal flash mem ory fig. 107. m37902f cc hp : block configuration of inter- nal flash memory page 102, fig. 10 7 m37902fe cg p, m 37902 fe c hp : b lock conf i gurat i on of inter nal fla sh memor y (deleted) fig. 110. m37902f gcg p, m37902f gc hp : block con- figuration of internal flash memory fig. 108. m37902f gc hp : block configuration of inter- nal flash memory page 102, fig. 10 8 m37902fh cg p, m37902f h c h p : bl ock config ur ation of inter nal fla sh memor y (deleted) page 103, right column, lines 15 to 1 7 area if the user use s the flash m emory se r ial i/o mode. note that, when the boot rom area i s read area if the user uses the flash memory serial i/o mode. addresses ffb0 16 to ffbf 16 are the reserved area for the serial programmer. therefore, when the user uses the flash memory serial i/o mode, do not program to this area. note that, when the boot rom area is read page 106, right column, after line 1 3 progr am the u ser rom area. program the user rom area. after reset removal, be sure not to change the status at pins md0 and md1. pi n co nnection of m37902f x cg p in f l ash m emory serial i/ o mode (deleted) page 106, fig. 114, notes 4 4: v alid onl y ?clear to ? . 4: valid only ?clear to ?. this bit 3 must be controll- ed with bit 1 = ?. page 107, left column, lines 16 to 2 0 ? command consists o f 8-bit u nits must be w r i t ten only to an e ven ad dr ess; ther efore, any data writt e n to an odd address will b e i nvalid. the write stat e ? command consisting of 8 bi t s must be written t o an even address; therefor e, any com mand written to an odd address will b e i nvalid. sin ce the write data at the 2nd cycle of a p r ogramm ing command consists of 16 bits, this data m ust be writt en to even and odd addr e sses. the write stat e page 107, right column, after line 2 4 request occu r rence. request occu r rence. in the c pu reprogr amming m od e, be sure no t to use the st p and wit instr uction s.
corrections and supplement ar y explanation for m37902fxc dat asheet (rev. b) no.10 page erro r correction (10/11) page 108, fig. 115 the c pu reprogramming mode select bit is set to 1? (writing of 0? writing of ?? writing of ? to the c pu reprogramming mode select bit. (writing of 0? writing of ?? page 108, software c ommands (d 8 ? 1 5 ) is ignored. (li nes 6, 7) (d 8 ? 1 5 ) is ignored. ( e xcept for the write data at the 2nd cycle of a page progr a m ming comm and.) (li nes 6, 7) page 109, page programming command (a f ter line 20) , the sam e way as bit 7 of the st a t us register . readi ng out the (li nes 4 to 7) , the sam e wayas bi t 7 of the status register. before execution of the next com mand, be su r e to ver ify that bi t 7 of t he status r egi st er ( s r.7) or the ry /by status bi t is set t o ?? (re ady ) . during t h e au t omatic progr amming operat i on, w r itin g of comm ands and access to the flash mem ory m ust not be perfor med. readi ng out the page 109, block erase command (li nes 20 to 2 3) , the same way as bit 7 of the status register. reading out the (li nes 20 to 2 3) , the same way as bit 7 of the status register. before execution of the next command, be sure to verify that bit 7 of the status register (sr.7) or the ry/by status bit is set to ??(ready). during the automatic erase operation, writing of commands and access to the flash memory must not be performed. reading out the page 111, erase all unlocked bloc k command (li nes 9 to 11 ) is al so report e d by a read of the st a t us register. when the lock bit (li nes 9 to 11 ) is al so report e d by a read of the st a t us register. during the autom atic erase oper a t i on (when the ry / b y status bi t = 0?) , writing of commands and access to the flash m e m ory m ust not be perfor med. when the lock bit page 108, p age progr amming co m mand (li nes 4 to 7) mode is m ai nt a ined. (a f ter line 20) mode is m ai nt a ined. i n continuou s program ming, if t h er e is no progr amming er ror, page program ming comm ands can be executed with the r ead status regi st er mode kept . (titll e) pag e p r og r am c om mand (41 16 ) (titll e) pag e p r og r amm i ng c om mand (41 16 ) page 111, data protec t function (block lock) (a f t er li ne 20) lock bit is terminated. (a f t er li ne 20) lock bit is terminated. to perform erase or programming, be sure to do one of the following. ?by executing the read lock bit status command, verify that the lock of the target block is invalid. ?set the lock bit invalidity select bit to ? to invalidate the lock. when the block erase or programming is performed with the lock valid, the erase status bit (sr.5) and program- ming status bit (sr.4) are set to 1 (terminated by error). page 114, ab solut e max im um ra tings 300 rating s s ymbol p d p ower di sspat i on p arameter uni t mw 400 rating s s ymbol p d p ower di sspat i on p arameter uni t mw t opr o perating t em perature t opr o perating ambien t temperature
corrections and supplement ar y explanation for m37902fxc dat asheet (rev. b) no.11 page erro r correction (11/11) t w(harf ) e xter nal cl ock page 123, t iming requ ir e m ents t w(half) e xter nal cl ock page 114, recommended operating conditions f( sys ) system clcok f requency f( f sys ) system clcok f requency f(f sys ) external clcok input frequency (note 2) f(x in ) external clcok input frequency (note 2) page 131, pa cke ge out li n e 100p 6s-a packege outline (deleted)

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